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參數(shù)資料
| 型號： | MT5C1008EC-55L |
| 廠商： | Austin Semiconductor, Inc |
| 英文描述： | 128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS |
| 中文描述： | 128K的× 8的SRAM具有雙芯片使可作為軍用規(guī)格 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 182K |
| 代理商： | MT5C1008EC-55L |
S R A M
MT5C1008
Austin Semiconductor, Inc.
MT5C1008
Rev. 6.5 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
NOTES
1.
All voltages referenced to V
SS
(GND).
2.
-2V for pulse width < 20ns
3.
I
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f = 1 Hz.
t
RC (MIN)
4.
This parameter is guaranteed but not tested.
5.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6.
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
allowing for actual tester RC time constant.
t
LZCE,
t
LZWE,
t
LZOE,
t
HZCE,
t
HZOE and
t
HZWE
7.
At any given temperature and voltage condition,
t
HZCE is less than
t
LZCE, and
t
HZWE is less than
t
LZWE and
t
HZOE is less than
t
LZOE.
WE\ is HIGH for READ cycle.
Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11.
12. CE2 timing is the same as CE1\ timing. The
waveform is inverted.
13. Chip enable (CE1\, CE2) and write enable (WE\) can
initiate and terminate a WRITE cycle.
8.
9.
t
RC = Read Cycle Time.
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
+5V
Q
255
30
480
5 pF
+5V
Q
255
480
123
123
123
123
1234
1234
1234
1234
DON’T CARE
UNDEFINED
LOW Vcc DATA RETENTION WAVEFORM
123456789
123456789
123456789
123456789
123456123
123456123
123456123
123456123
123456789
123456789
123456789
123456789
123456123
123456123
123456123
123456123
DATA RETENTION MODE
V
DR
> 2V
4.5V
4.5V
V
DR
t
CDR
t
R
<V
SS
+ 0.2V
V
IH
V
IL
V
IH
V
IL
V
CC
CE1\
CE2
SYMBOL
V
DR
MIN
2
MAX
---
UNITS
V
NOTES
Data Retention Current
CE\ > (V
CC
- 0.2V)
V
IN
> (V
CC
- 0.2V)
or < 0.2V, f=0
V
CC
= 2V
I
CCDR
1.0
mA
Chip Deselect to Data
Retention Time
Operation Recovery Time
t
CDR
0
---
ns
4
t
R
t
RC
ns
4, 11
CONDITIONS
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