參數(shù)資料
型號: MT58L128V18FT-6.8
廠商: Micron Technology, Inc.
英文描述: 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM
中文描述: 2MB的:128K的× 18,64K的x 32/36流通過SYNCBURST的SRAM
文件頁數(shù): 15/24頁
文件大?。?/td> 488K
代理商: MT58L128V18FT-6.8
15
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_2.p65
Rev. 6/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
FLOW-THROUGH SYNCBURST SRAM
READ TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
BWa#-BWd#
Q
High-Z
tKQLZ
tKQX
tKQ
ADV#
tOEHZ
tKQ
Single READ
BURST
READ
tOEQ
tOELZ
tKQHZ
Burst wraps around
to its initial state.
tAAH
tAAS
tWH
tWS
tADSH
tADSS
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
A2
(NOTE 1)
BWE#, GW#,
ADV# suspends burst.
DON
T CARE
UNDEFINED
Deselect Cycle
(Note 4)
NOTE:
1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
4. Outputs are disabled
t
KQHZ after deselect.
-6.8
-7.5
-8.5
-10
SYMBOL
t
AS
t
ADSS
t
AAS
t
WS
t
CES
t
AH
t
ADSH
t
AAH
t
WH
t
CEH
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
1.8
2.0
2.0
1.8
2.0
2.0
1.8
2.0
2.0
1.8
2.0
2.0
1.8
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
READ TIMING PARAMETERS
-6.8
-7.5
-8.5
-10
SYMBOL
t
KC
f
KF
t
KH
t
KL
t
KQ
t
KQX
t
KQLZ
t
KQHZ
t
OEQ
t
OELZ
t
OEHZ
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
8.0
8.8
10.0
125
113
1.8
1.9
1.9
1.8
1.9
1.9
6.8
7.5
1.5
1.5
3.0
1.5
1.5
1.5
3.8
4.2
3.8
4.2
0
0
0
3.8
4.2
15
ns
100
66
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.0
4.0
8.5
10.0
3.0
1.5
5.0
5.0
5.0
5.0
0
5.0
5.0
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