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參數(shù)資料
| 型號： | MT55L128V32F1 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2.5V I/O， 128K x 32，F(xiàn)low-Through ZBT SRAM(2.5V輸入/輸出,4Mb流通式同步靜態(tài)存儲器) |
| 中文描述： | 2.5VI / O的128K的× 32，流量通過ZBT SRAM的電壓（2.5V輸入/輸出，4Mb的流通式同步靜態(tài)存儲器） |
| 文件頁數(shù)： | 3/25頁 |
| 文件大小： | 451K |
| 代理商： | MT55L128V32F1 |
3
4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM
MT55L256L18F1_2.p65
–
Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH ZBT SRAM
PRELIMINARY
one, the address is present on rising edge one. BYTE
WRITEs need to be asserted on the same cycle as the
address. The write data associated with the address is
required one cycle later, or on the rising edge of clock
cycle two.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa#
controls DQa pins; BWb# controls DQb pins; BWc#
controls DQc pins; and BWd# controls DQd pins. Cycle
types can only be defined when an address is loaded,
i.e., when ADV/LD# is LOW. Parity/ECC bits are only
available on the x18 and x36 versions.
Micron’s 4Mb ZBT SRAMs operate from a +3.3V V
DD
power supply, and all inputs and outputs are LVTTL-
compatible. Users can choose either a 2.5V or 3.3V I/O
version. The device is ideally suited for systems requir-
ing high bandwidth and zero bus turnaround delays.
refer (www.micronsemi.com/datasheets/zbtds.html
) for the
Micron’s siteGENERAL DESCRIPTION (continued)
(ADV/LD#), synchronous clock enable (CKE#), byte
write enables (BWa#, BWb#, BWc#, and BWd#) and
read/write (R/W#).
Asynchronous inputs include the output enable
(OE#, which may be tied LOW for control signal mini-
mization), clock (CLK) and snooze enable (ZZ, which
may be tied LOW if unused). There is also a burst mode
pin (MODE) that selects between interleaved and linear
burst modes. MODE may be tied HIGH, LOW or left
unconnected if burst is unused. The flow-through data-
out (Q) is enabled by OE#. WRITE cycles can be from
one to four bytes wide as controlled by the write control
inputs.
All READ, WRITE and DESELECT cycles are initiated
by the ADV/LD# input. Subsequent burst addresses can
be internally generated as controlled by the burst
advance pin (ADV/LD#). Use of burst mode is optional.
It is allowable to give an address for each individual
READ and WRITE cycle. BURST cycles wrap around
after the fourth access from a base address.
To allow for continuous, 100 percent use of the data
bus, the flow-through ZBT SRAM uses a LATE WRITE
cycle. For example, if a WRITE cycle begins in clock cycle
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT55L128V36F1 | 2.5V I/O，128K x 36，F(xiàn)low-Through ZBT SRAM(2.5V輸入/輸出,4Mb流通式同步靜態(tài)存儲器) |
| MT55L128L32P1 | 3.3V I/O，128K x 32，F(xiàn)low-Through ZBT SRAM(3.3V輸入/輸出,4Mb流通式同步靜態(tài)存儲器) |
| MT55L128L36P1 | 3.3V I/O，128K x 36，F(xiàn)low-Through ZBT SRAM(3.3V或輸入/輸出,4Mb流通式同步靜態(tài)存儲器) |
| MT55L128V32P1 | 2.5V I/O，128K x 32，F(xiàn)low-Through ZBT SRAM(2.5V輸入/輸出,4Mb流通式同步靜態(tài)存儲器) |
| MT55L128V36P1 | 2.5V I/O，128K x 36，F(xiàn)low-Through ZBT SRAM(2.5V輸入/輸出,4Mb流通式同步靜態(tài)存儲器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT55L128V32F1T-10 | 制造商:Micron Technology Inc 功能描述: |
| MT55L128V36P1T-10 | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55L128V36P1T10A | 制造商:Micron Technology Inc 功能描述: |
| MT55L128V36P1T-6 | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V |
| MT55L128V36P1T-7.5 | 制造商:Micron Technology Inc 功能描述: |
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