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參數(shù)資料
| 型號： | MT46V64M4FG-75Z |
| 元件分類： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| 封裝： | 8 X 14 MM, PLASTIC, FBGA-60 |
| 文件頁數(shù)： | 37/83頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | MT46V64M4FG-75Z |
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256Mb: x4, x8, x16
DDR SDRAM
09005aef8076894f
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MBDDRx4x8x16_2.fm - Rev. K 9/04 EN
42
2003 Micron Technology, Inc. All rights reserved.
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 7 on page 41) and after
tXSNR has been met (if the
previous state was self refresh).
2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are
those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below.
3. Current state definitions:
Idle:The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no regis-
ter accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
nated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been ter-
minated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP com-
mands, or allowable commands to the other bank should be issued on any clock edge occurring during these states.
Allowable commands to the other bank are determined by its current state and Table 8, Truth Table – Current State
Bank n – Command to Bank n, on page 42 and according to Table 9, Truth Table – Current State Bank n– Command to
Bank m, on page 44.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the
bank will be in the idle state.
Row
Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the
bank will be in the “row active” state.
Read w/Auto-Precharge
Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has
beenmet. Once tRP is met, the bank will be in the idle state.
Write w/Auto- Precharge
Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has
been met. Once tRP is met, the bank will be in the idle state.
Table 8:
Truth Table – Current State Bank n – Command to Bank n
Notes: 1–6; notes appear below and on next page
CURRENT STATE
CS#
RAS#
CAS#
WE#
COMMAND/ACTION
NOTES
Any
H
X
LH
H
NO OPERATION (NOP/continue previous operation)
Idle
L
H
ACTIVE (select and activate row)
LL
L
H
AUTO REFRESH
7
LL
L
LOAD MODE REGISTER
7
Row Active
L
H
L
H
READ (select column and start READ burst)
10
LH
L
WRITE (select column and start WRITE burst)
10
LL
H
L
PRECHARGE (deactivate row in bank or banks)
8
Read
(Auto-
Precharge
Disabled)
LH
L
H
READ (select column and start new READ burst)
10
LH
L
WRITE (select column and start WRITE burst)
10, 12
LL
H
L
PRECHARGE (truncate READ burst, start PRECHARGE)
8
LH
H
L
BURST TERMINATE
9
Write
(Auto-
Precharge
Disabled)
LH
L
H
READ (select column and start READ burst)
10, 11
LH
L
WRITE (select column and start new WRITE burst)
10
LL
H
L
PRECHARGE (truncate WRITE burst, start PRECHARGE)
8, 11
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V64M4FJ-6 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M4FJ-6T | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M4FJ-75Z | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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