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參數(shù)資料
| 型號： | MT46V32M4TG-8L |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 38/68頁 |
| 文件大?。?/td> | 2547K |
| 代理商： | MT46V32M4TG-8L |
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38
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65
–
Rev. C; Pub. 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
DDR SDRAM
PRELIMINARY
TRUTH TABLE 2
–
CKE
(Notes: 1-4)
CKE
n-1
CKE
n
L
CURRENT STATE
Power-Down
Self Refresh
Power-Down
Self Refresh
All Banks Idle
Bank(s) Active
All Banks Idle
COMMAND
n
X
X
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
AUTO REFRESH
ACTION
n
Maintain Power-Down
Maintain Self Refresh
Exit Power-Down
Exit Self Refresh
Precharge Power-Down Entry
Active Power-Down Entry
Self Refresh Entry
NOTES
L
L
H
5
H
L
NOTE:
1. CKE
n
is the logic state of CKE at clock edge
n
; CKE
n-1
was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge
n
.
3. COMMAND
is the command registered at clock edge
n
, and ACTION
n
is a result of COMMAND
n
.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT or NOP commands should be issued on any clock edges occurring during the
t
XSR period. A minimum of 200
clock cycles is needed before applying a READ command for the DLL to lock.
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