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| 型號： | MT46V32M4TG-75ZL |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 16/68頁 |
| 文件大小： | 2547K |
| 代理商： | MT46V32M4TG-75ZL |
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16
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65
–
Rev. C; Pub. 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
DDR SDRAM
PRELIMINARY
Operations
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be
issued to a bank within the DDR SDRAM, a row in that
bank must be
“
opened.
”
This is accomplished via the
ACTIVE command, which selects both the bank and
the row to be activated, as shown in Figure 4.
After a row is opened with an ACTIVE command,
a READ or WRITE command may be issued to that
row, subject to the
t
RCD specification.
t
RCD (MIN)
should be divided by the clock period and rounded up
to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a
READ or WRITE command can be entered. For ex-
ample, a
t
RCD specification of 20ns with a 133 MHz
clock (7.5ns period) results in 2.7 clocks rounded to 3.
This is reflected in Figure 5, which covers any case where
2 <
t
RCD (MIN)/
t
CK
≤
3. (Figure 5 also shows the same
case for
t
RCD; the same procedure is used to convert
other specification limits from time units to clock
cycles).
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been
“
closed
”
(precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by
t
RC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
t
RRD.
Figure 5
Example: Meeting
t
RCD (
t
RRD) MIN When 2 <
t
RCD (
t
RRD) MIN/
t
CK < 3
Figure 4
Activating a Specific Row in
a Specific Bank
CS#
WE#
CAS#
RAS#
CKE
A0-A11
RA
RA = Row Address
BA = Bank Address
HIGH
BA0,1
BA
CK
CK#
COMMAND
BA0, BA1
ACT
ACT
NOP
tRRD
tRCD
CK
CK#
Bank
x
Bank
y
A0-A11
Row
Row
NOP
RD/WR
NOP
Bank
y
Col
NOP
T0
T1
T2
T3
T4
T5
T6
T7
DON
’
T CARE
NOP
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PDF描述 |
|---|---|
| MT46V32M4TG-8 | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-8L | DOUBLE DATA RATE DDR SDRAM |
| MT46V4M32 | DOUBLE DATA RATE DDR SDRAM |
| MT46V4M32LG | I.MX31 LITE KIT |
| MT46V64M4 | 16 Meg x 4 x 4 banks DDR SDRAM(16M x 4 x 4組,雙數(shù)據(jù)速率同步動態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V32M4TG-8 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-8L | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M8 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M82ZZ5-75 ES | 制造商:Micron Technology Inc 功能描述:32MX8 SDRAM DDR PLASTIC PBF FBGA 2.5V - Trays |
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