參數(shù)資料
型號： MT46V32M4-1
廠商： Micron Technology, Inc.
英文描述： DOUBLE DATA RATE DDR SDRAM
中文描述： 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存
文件頁數(shù)： 62/68頁
文件大?。?/td> 2547K
代理商： MT46V32M4-1
62
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65
–
Rev. C; Pub. 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
DDR SDRAM
PRELIMINARY
SELF REFRESH MODE
CK
1
CK#
COMMAND
4
NOP
AR
ADDR
CKE
1
VALID
DQ
DM
DQS
VALID
NOP
NOTE
: 1. Clock must be stable before exiting self refresh mode. That is, the clock must be cycling within
specifications by Ta0.
2. Device must be in the all banks idle state prior to entering self refresh mode.
3.
t
XSNR is required before any non-READ command can be applied, and
t
XSRD (200 cycles of CK)
is required before a READ command can be applied.
4. AR = AUTO REFRESH command.
t
RP
2
t
CH
t
IH
t
CL
tCK
t
IS
tXSNR/
tXSRD
3
t
IS
t
IH
t
IS
tIS
tIH
tIS
Enter Self Refresh Mode
Exit Self Refresh Mode
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T0
T1
Ta0
1
Tb0
Ta1
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DON
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TIMING PARAMETERS
-75Z
-75
-8
SYMBOL
t
IS
t
RP
t
XSNR
t
XSRD
MIN
1
20
75
200
MAX
MIN
1
20
75
200
MAX
MIN
1.1
20
80
200
MAX
UNITS
ns
ns
ns
t
CK
-75Z
-75
-8
SYMBOL
t
CH
t
CL
t
CK (2.5)
t
CK (2)
t
IH
MIN
0.45
MAX
0.55
0.45
13
13
MIN
0.45
0.550.45
7.5
10
1
MAX
0.55
0.55
13
13
MIN
0.45
0.45
8
10
1.1
MAX
0.55
0.55
13
13
UNITS
t
CK
t
CK
ns
ns
ns
7.5
7.5
1
相關(guān)PDF資料
PDF描述
MT46V32M4TG-75 DOUBLE DATA RATE DDR SDRAM
MT46V32M4TG-75L DOUBLE DATA RATE DDR SDRAM
MT46V32M4TG-75Z DOUBLE DATA RATE DDR SDRAM
MT46V32M4TG-75ZL DOUBLE DATA RATE DDR SDRAM
MT46V32M4TG-8 DOUBLE DATA RATE DDR SDRAM
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