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參數(shù)資料
| 型號(hào)： | MT2D18 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 1 Meg x 8 DRAM Module(5V，1M x 8 動(dòng)態(tài)RAM模塊) |
| 中文描述： | 1梅格× 8內(nèi)存模塊（5V的，100萬(wàn)× 8動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 2/11頁(yè) |
| 文件大小： | 174K |
| 代理商： | MT2D18 |
MT2D18
DM01.pm5 – Rev. 2/95
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1995, Micron Technology, Inc.
2
MT2D18
1 MEG x 8 DRAM MODULE
OBSOLETE
TRUTH TABLE
ADDRESSES
t
R
X
ROW
ROW
ROW
n/a
ROW
n/a
ROW
ROW
ROW
X
DATA-IN/OUT
DQ1-DQ8
High-Z
Data-Out
Data-In
Data-Out
Data-Out
Data-In
Data-In
High-Z
Data-Out
Data-In
High-Z
FUNCTION
Standby
READ
EARLY WRITE
FAST-PAGE-MODE
READ
FAST-PAGE-MODE
WRITE
R
A
/
S-ONLY REFRESH
HIDDEN
REFRESH
CBR REFRESH
R
A
//
S
H
L
L
L
L
L
L
L
C
A
//
S
H
>
X
L
L
H
>
L
H
>
L
H
>
L
H
>
L
H
L
L
L
W
//
E
X
H
L
H
H
L
L
X
H
L
H
t
C
X
COL
COL
COL
COL
COL
COL
n/a
COL
COL
X
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
READ
WRITE
L
>
H
>
L
L
>
H
>
L
H
>
L
REFRESH
Returning
R
A
/
S and
C
A
/
S HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the
R
A
/
S HIGH time. Memory cell data is retained in its
correct state by maintaining power and executing any
R
A
/
S cycle (READ, WRITE) or
R
A
/
S refresh cycle (
R
A
/
S
ONLY, CBR or HIDDEN) so that all 1,024 combinations of
R
A
/
S addresses (A0-A9) are executed at least every 16ms
regardless of sequence.
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
WE
Vcc
Vss
U1-U2 = MT4C4001JDJ
RAS
CAS
WE
OE
U1
RAS
CAS
WE
OE
Vcc
U2
Vss
A0-A9
4
4
DQ1-DQ4
DQ5-DQ8
Vcc
Vss
A0-A9
DQ1-DQ4
A0-A9
DQ1-DQ4
10
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