參數(shù)資料
型號(hào)： MT28C128564W30DBW-F706P85KBTWT
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA77
封裝： LEAD FREE, FBGA-77
文件頁(yè)數(shù)： 2/15頁(yè)
文件大?。?/td> 158K
代理商： MT28C128564W30DBW-F706P85KBTWT
128Mb MULTIBANK BURST FLASH
32Mb/64Mb ASYNC/PAGE CellularRAM COMBO
PRELIMINARY
09005aef80b10a55
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C128564W18D_C.fm - Rev. C, Pub 10/03 EN
10
2003 Micron Technology. Inc. All rights reserved.
Boot Configurations
The possible configurations for Flash die are shown
in Table 2 below. This table shows the possible config-
urations of the two Flash devices for either top boot or
bottom boot: F_CE1# and F_CE2# indicate to which
Flash die the configuration is referred.
MultiChip Packaging Considerations
Multichip packaging presents unique chal-
lenges when controlling complex memory devices.
The
MT28C128532W18/W30D
and
MT28C128564W18/W30D
devices
combine
two
Micron Flash devices with a single CellularRAM
device.
Unique IDs, State Machines, and
Registers
Each Flash device has a separate command state
machine (CSM) and status register (SR) and read con-
figuration register (RCR). The RCR settings are sepa-
rate and can be different for the upper and lower
device. Each Flash device has its own OTP, CFI, and
device code. Depending on the boot configuration of
each Flash device, the OTP, CFI, and device code infor-
mation may differ.
Both Flash devices will share the same ManID,
either Micron (0x2Ch) or Intel (0x89h), which is
defined by the part number. (See Figure 4 on page 8.)
The CellularRAM has a configuration register (CR)
that defines how the device performs self refresh.
Command Codes
All Flash command codes are independent
within each device. Care must be taken when
crossing the array boundary between the upper
and lower Flash and the CellularRAM to ensure
that only one device is enabled at one time.
In a two-cycle command sequence such as word
program (0x40/data), it is required that both com-
mands be issued to the same device.
It is not recommended that simultaneous
READ, simultaneous WRITE, or simultaneous
ERASE operations occur on both devices.
READ Operation
Page and burst read modes are limited to the
address boundaries of each device. A new page/burst
operation must be started when crossing a device
boundary.
Flash Reset
The reset control is shared by both Flash die.
Bringing RST# control LOW will reset both the
upper and lower device.
Power Consumption
Multiple chip packaging requires that power
calculations consider the active operation of the
upper and lower Flash as well as that of the Cellu-
larRAM. Total power consumed will be the sum of
the currents associated with the state of each
device.
Table 2:
Possible Boot Configurations
for Flash Die
CONFIGURATION
F_CE2#
F_CE1#
ORDER
CODE
Top/Top
Top
TT
Top/Bottom
Top
Bottom
TB
Bottom/Top
Bottom
Top
BT
Bottom/Bottom
Bottom
BB
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