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參數(shù)資料
| 型號： | MT16LD1664A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DRAM MODULE |
| 中文描述： | DRAM模塊 |
| 文件頁數(shù)： | 6/27頁 |
| 文件大小： | 518K |
| 代理商： | MT16LD1664A |
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6
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65
–
Rev. 2/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
PIN DESCRIPTIONS
PIN NUMBERS
30, 45, 114, 129
SY MBOL
RAS0#-RAS3#
TY PE
Input
DESCRIPTION
Row-Address Strobe: RAS# is used to clock-in the
row-address bits. Two RAS# inputs allow for one x64
bank or two x32 banks.
Column-Address Strobe: CAS# is used to clock-in the
column-address bits, enable the DRAM output
buffers and strobe the data inputs on WRITE cycles.
Eight CAS# inputs allow byte access control for any
memory bank configuration.
Write Enable: WE# is the READ/WRITE control for the
DQ pins. WE0# controls DQ0-DQ31. WE2# controls
DQ32-DQ63. If WE# is LOW prior to CAS# going
LOW, the access is an EARLY WRITE cycle. If WE# is
HIGH while CAS# is LOW, the access is a READ cycle,
provided OE# is also LOW. If WE# goes LOW after
CAS# goes LOW, then the cycle is a LATE WRITE cycle.
A LATE WRITE cycle is generally used in conjunction
with a READ cycle to form a READ-MODIFY-WRITE
cycle.
Output Enable: OE# is the input/output control for
the DQ pins. OE0# controls DQ0-DQ31. OE2# controls
DQ32-DQ63. These signals may be driven, allowing
LATE WRITE cycles.
Address Inputs: These inputs are multiplexed and
clocked by RAS# and CAS#.
Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs
to the addressed DRAM location. BYTE WRITEs may
be performed by using the corresponding CAS#
select (x64 mode only). For READ access cycles,
DQ0-DQ63 act as outputs for the addressed DRAM
location.
Reserved for Future Use: These pins should be left
unconnected.
Power Supply: +3.3V ±0.3V.
28, 29, 46, 47, 112,
113, 130, 131
CAS0#-CAS7#
Input
27, 48
WE0#, WE2#
Input
31, 44
OE0#, OE2#
Input
33-38, 117-122
A0-A11
Input
2-5, 7-11, 13-17, 19-20,
55-58, 60, 65-67, 69-72,
74-77, 86-89,91-95,
97-101, 103-104,
139-142, 144, 149-151,
153-156, 158-161
42, 62, 111, 115,
125-126, 128, 132, 146
6, 18, 26, 40, 41, 49, 59,
73, 84, 90, 102, 110,
124, 133, 143, 157, 168
1, 12, 23, 32, 43, 54, 64,
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
82
DQ0-DQ63
Input/
Output
RFU
–
V
DD
Supply
V
SS
Supply
Ground.
SDA
Input/Output
Serial Presence-Detect Data. SDA is a bidirectional pin
used to transfer addresses and data into and data out
of the presence-detect portion of the module.
Serial Clock for Presence-Detect. SCL is used to
synchronize the presence-detect data transfer to and
from the module.
Presence-Detect Address Inputs. These pins are used
to configure the presence-detect device.
83
SCL
Input
165-167
SA0-SA2
Input
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