Data Sheet #:
TM027 P
age
3
of
16
Rev:
P05
Date:
12 / 02 / 02
Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
NOTES:
1.0:
Stresses beyond those listed under Absolute Maximum Rating may cause damage
to the device. Operation beyond Recommended Conditions is not implied.
2.0:
Logic is 3.3V CMOS
3.0 GR-1244-CORE 3.2.1
Recommended Operating Conditions
Table 3
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
V
cc
V
TH
V
IH
V
IL
t
C
IN
V
OH
Power supply voltage
4.75
5.00
5.25
Volts
Reset threshold voltage
4.25
4.5
Volts
High level input voltage - TTL
2.0
V
CC
0.8
Volts
Low level input voltage - TTL
0
Volts
Input signal transition - TTL
250
ns
Input capacitance
15
pF
High level output voltage,
I
OH
= -4.0mA, V
CC
= min.
Low level output voltage,
I
OL
= 12.0 mA, V
CC
= min.
Clock output transition time
2.4
5.25
Volts
2.0
V
OL
0.4
Volts
t
TRANS
t
PULSE
4.0
ns
8kHz input reference pulse
width( positive or negative)
30
ns
T
OP
Operating temperature
0
70
°C
Specifications
Table 4
Parameter
Specifications
Notes
Frequency Range (Sync_Out)
8 kHz to 77.76 MHz
Frequency Range (Opt_Out)
8 kHz to 77.76 MHz
Supply Current
250 mA typical, 400 mA during warm-up (Maximum)
Timing Reference Inputs
8 kHz - 19.44 MHz
3.0
Jitter, Wander and Phase Transient Tolerances
GR-1244-CORE 4.2-4.4, GR-253-CORE 5.4.4.3.6
Wander Generation
GR-1244-CORE 5.3, GR-253-CORE 5.4.4.3.2
Wander Transfer
GR-1244-CORE 5.4
Jitter Generation
GR-1244-CORE 5.5, GR-253-CORE 5.6.2.3
Jitter Transfer
GR-1244-CORE 5.5, GR-253-CORE 5.6.2.1
Phase Transients
GR-1244-CORE 5.6, GR-253-CORE 5.4.4.3.3
Free Run Accuracy
4.6 ppm over T
OP
±0.37 ppm for initial 24 hrs
Hold Over Stability
4.0
Inital Offset
±0.05 ppm
Temperature
±0.28 ppm
Drift
±0.04 ppm
Maximum Hold Over History
40 seconds
Pull-in/ Hold-in Range
±13.8 ppm minimum
5.0
Lock Time
30 seconds typical
DPLL Bandwidth
< 0.1 Hz
4.0:
Hold Over stability is the cumulative fractional frequency offset as described by
GR-1244-CORE, 5.2
Pull-in Range is the maximum frequency deviation from nominal clock rate on the
reference inputs to the timing module that can be overcome to pull into synchronization
with the reference
5.0: