MSP50C32, MSP50C33, MSP50C34
MSP50P34, MSP50C37, MSP50P37
MIXED-SIGNAL PROCESSORS
SPSS019A – MAY 1997 – REVISED OCTOBER 1998
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MSP50x37 electrical characteristics over recommended ranges of supply voltage and operating
free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VT
Positive going threshold voltage (INIT)
VDD = 4.5 V
2.7
V
VT+
Positive-going threshold voltage (INIT)
VDD = 6 V
3.65
V
VT
Negative going threshold voltage (INIT)
VDD = 4.5 V
2.3
V
VT–
Negative-going threshold voltage (INIT)
VDD = 6 V
3.15
V
Vh
Hysteresis ( VT
VT ) (INIT)
VDD = 4.5 V
0.4
V
Vhys
Hysteresis (VT+ – VT– ) (INIT)
VDD = 6 V
0.5
V
IIkg
Input leakage current (except for OSC IN)
1
A
Istandby
Standby current (INIT low, SETOFF)
10
A
I
Supply current
Power amplifier is on
25
mA
IDD
Supply current
Power amplifier is off
10
mA
VDD = 4 V,
VOH = 3.5 V
– 4
–6
VDD = 5 V,
VOH = 4.5 V
–5
–7.5
mA
IOH
High level output current (PA PB PD)
VDD = 6 V,
VOH = 5.5 V
–6
– 9.2
IOH
High-level output current (PA, PB, PD)
VDD = 4 V,
VOH = 2.65 V
– 8
–13
VDD = 5 V,
VOH = 3.33 V
–14
– 20
mA
VDD = 6 V,
VOH = 4 V
– 20
– 29
VDD = 4 V,
VOL = 0.5 V
20
28
VDD = 5 V,
VOL = 0.5 V
26
34
mA
IOL
Low level output current (PA4
PA7)
VDD = 6 V,
VOL = 0.5 V
30
39
IOL
Low-level output current (PA4 – PA7)
VDD = 4 V,
VOL = 1.33 V
40
54
VDD = 5 V,
VOL = 1.67 V
60
74
mA
VDD = 6 V,
VOL = 2 V
82
103
VDD = 4 V,
VOL = 0.5 V
10
17
VDD = 5 V,
VOL = 0.5 V
13
20
mA
IOL
Low level output current (PA0
PA3 PB PD))
VDD = 6 V,
VOL = 0.5 V
15
25
IOL
Low-level output current (PA0 – PA3, PB, PD))
VDD = 4 V,
VOL = 1.33 V
20
32
VDD = 5 V,
VOL = 1.67 V
30
52
mA
VDD = 6 V,
VOL = 2 V
41
71
Pullup resistance
Resistors selected by software and
connected between terminal and VDD
15
30
60
k
f
(l
)
Oscillator freq enc
VDD = 5 V,
TA = 25°C,
14 89
15 36
15 82
MHz
fosc(low)
Oscillator frequency
Target frequency = 15.36 MHz
14.89
15.36
15.82
MHz
f
(hi h)
O
ill t
f
VDD = 5 V,
TA = 25°C,
18 62
19 2
19 77
MHz
fosc(high)
Oscillator frequency
Target frequency = 19.2 MHz
18.62
19.2
19.77
MHz
Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output
and other outputs are open circuited.
The frequency of the internal clock has a temperature coefficient of approximately – 0.2 % /
°C and a VDD coefficient of approximately ±1.4%/V.