
MSP430C33x, MSP430P337A
MIXED SIGNAL MICROCONTROLLERS
SLAS227A – OCTOBER 1999 – REVISED JUNE 2000
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Timer/Port
The Timer/Port module has two 8-Bit Timer/Counters, an input that triggers one counter, and six digital outputs
with 3-state capability. Both counters have an independent clock selector for selecting an external signal or one
of the internal clocks (ACLK or MCLK). One of the counters has an extended control capability to halt, count
continuously, or gate the counter by selecting one of two external signals. This gate signal sets the interrupt flag
if an external signal is selected and the gate stops the counter.
Both timers can be read to and written from by software. The two 8-Bit Timer/Counters can be cascaded to form
a 16-bit counter. A common interrupt vector is implemented. The interrupt flag can be set by three events in the
8-Bit Timer/Counter mode (gate signal or overflow from the counters) or by two events in the 16-bit counter mode
(gate signal or overflow from the MSB of the cascaded counter).
slope A/D conversion
Slope A/D conversion is accomplished with the Timer/Port module using external resistor(s) for reference (Rref),
using external resistor(s) to the measured (Rmeas), and an external capacitor. The external components are
driven by software in such a way that the internal counter measures the time that is needed to charge or
discharge the capacitor. The reference resistor’s (Rref) charge or discharge time is represented by Nref counts.
The unknown resistors (Rmeas) charge or discharge time is represented by Nmeas counts. The unknown
resistor’s value Rmeas is the value of Rref multiplied by the relative number of counts (Nmeas/Nref). This value
determines resistive sensor values that correspond to the physical data, for example temperature, when an NTC
or PTC resistor is used.
Timer_A
The Timer_A module (see Figure1) offers one sixteen bit counter and five capture/compare registers. The timer
clock source can be selected to come from an external source TACLK (SSEL=0), the ACLK (SSEL=1), or
MCLK (SSEL=2 or SSEL=3). The clock source can be divided by one, two, four, or eight. The timer can be fully
controlled (in word mode) since it can be halted, read, and written. It can be stopped or run continuously. It can
count up or count up/down using one compare block to determine the period. The five capture/compare blocks
are configured by the application software to run in either capture or compare mode.
The capture mode is primarily used to measure external or internal events with any combination of positive,
negative, or both edges of the clock. The clock can also be stopped in capture mode by software. One external
event (CCISx=0) per capture block can be selected. If CCISx=1, the ACLK is the capture signal; and if CCISx=2
or CCISx=3, software capture is chosen.
The compare mode is primarily used to generate timing for the software or application hardware or to generate
pulse-width modulated output signals for various purposes like D/A conversion functions or motor control. An
individual output module, which can run independently of the compare function or is triggered in several ways,
is assigned to each of the five capture/compare registers.
Two interrupt vectors are used by the Timer_A module. One individual vector is assigned to capture/compare
block CCR0 and one common interrupt vector is assigned to the timer and the other four capture/compare
blocks. The five interrupt events using the common vector are identified by an individual interrupt vector word.
The interrupt vector word is used to add an offset to the program counter to continue the interrupt handler
software at the correct location. This simplifies the interrupt handler and gives each interrupt event the same
interrupt handler overhead of 5 cycles.