參數(shù)資料
型號(hào)： MSP430F4132IRGZT
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PQCC48
封裝： GREEN, PLASTIC, MS-026, QFN-48
文件頁(yè)數(shù)： 44/82頁(yè)
文件大小： 1562K
代理商： MSP430F4132IRGZT
MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
49
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
flash memory
PARAMETER
TEST
CONDITIONS
VCC
MIN
NOM
MAX
UNIT
VCC(PGM/
ERASE)
Program and Erase supply voltage
2.2
3.6
V
fFTG
Flash Timing Generator frequency
257
476
kHz
IPGM
Supply current from DVCC during program
2.5V/3.6V
3
5
mA
IERASE
Supply current from DVCC during erase
2.5V/3.6V
3
7
mA
tCPT
Cumulative program time
seeNote1
2.5V/3.6V
10
ms
tCMErase
Cumulative mass erase time
seeNote2
2.5V/3.6V
200
ms
Program/Erase endurance
104
105
cycles
tRetention
Data retention duration
TJ =25C
100
years
tWord
Word or byte program time
35
tBlock, 0
Block program time for 1st byte or word
30
tBlock, 1-63
Block program time for each additional byte or word
see Note 3
21
t
tBlock, End
Block program end-sequence wait time
seeNote3
6
tFTG
tMass Erase
Mass erase time
5297
tSeg Erase
Segment erase time
4819
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64--byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297x1 / fFTG, max = 5297 x 1 / 476 kHz).
To achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is
met. (A worst case minimum of 19 cycles is required.)
3. These values are hardwired into the Flash Controller’s state machine (tFTG =1/fFTG).
JTAG and Spy-Bi-Wire interface
PARAMETER
TEST
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V/3 V
0
8
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V/3 V
0.025
15
us
tSBW,En
Spy-Bi-Wire enable time,
TEST high to acceptance of first clock edge
(see Note 1)
2.2 V/3 V
1
us
tSBW,Ret
Spy-Bi-Wire return to normal operation time
2.2 V/3 V
15
100
us
f
TCK input frequency (see Note 2)
2.2 V
0
5
MHz
fTCK
TCK input frequency (see Note 2)
3V
0
10
MHz
RInternal
Internal pulldown resistance on TEST
2.2 V/3 V
25
60
90
k
NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high
before applying the first SBWCLK clock edge.
2. fTCK may be restricted to meet the timing requirements of the module selected.
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