參數資料
型號: MSP430F2274MRHAEP
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, RISC MICROCONTROLLER, PQCC40
封裝: GREEN, PLASTIC, MO-220VJJD-2, VQFN-40
文件頁數: 78/79頁
文件大?。?/td> 1274K
代理商: MSP430F2274MRHAEP
SLAS614C – SEPTEMBER 2008 – REVISED JULY 2010
www.ti.com
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh–0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed), the CPU goes
into LPM4 immediately after power up.
SYSTEM
INTERRUPT SOURCE
INTERRUPT FLAG
WORD ADDRESS
PRIORITY
INTERRUPT
Power up
PORIFG
External reset
RSTIFG
Watchdog
WDTIFG
Reset
0FFFEh
31, highest
Flash key violation
KEYV
PC out-of-range(1)
(2)
NMI
NMIIFG
(non)-maskable,
Oscillator fault
OFIFG
(non)-maskable,
0FFFCh
30
Flash memory access violation
ACCVIFG (2) (3)
(non)-maskable
Timer_B3
TBCCR0 CCIFG(4)
maskable
0FFFAh
29
TBCCR1 and TBCCR2
Timer_B3
maskable
0FFF8h
28
CCIFGs, TBIFG(2) (4)
0FFF6h
27
Watchdog Timer
WDTIFG
maskable
0FFF4h
26
Timer_A3
TACCR0 CCIFG(4)
maskable
0FFF2h
25
TACCR1 CCIFG,
Timer_A3
TACCR2 CCIFG,
maskable
0FFF0h
24
TAIFG (2) (4)
USCI_A0/USCI_B0 Receive
UCA0RXIFG, UCB0RXIFG(2)
maskable
0FFEEh
23
USCI_A0/USCI_B0 Transmit
UCA0TXIFG, UCB0TXIFG(2)
maskable
0FFECh
22
ADC10
ADC10IFG(4)
maskable
0FFEAh
21
0FFE8h
20
I/O Port P2 (eight flags)
P2IFG.6 to P2IFG.7(2) (4)
maskable
0FFE6h
19
I/O Port P1 (eight flags)
P1IFG.0 to P1IFG.7(2) (4)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
(5)
0FFDEh
15
(6)
0FFDCh ... 0FFC0h
14 ... 0, lowest
(1)
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h–01FFh) or from
within unused address range.
(2)
Multiple source flags
(3)
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit disables an interrupt event.
(4)
Interrupt flags are located in the module.
(5)
This location is used as bootstrap loader security key (BSLSKEY). A 0AA55h at this location disables the BSL completely. A zero (0h)
disables the erasure of the flash if an invalid password is supplied.
(6)
The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
8
Copyright 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): MSP430F2274-EP
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