參數(shù)資料
型號: MSP430F2002IRSA
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQCC16
封裝: PLASTIC, QFN-16
文件頁數(shù): 5/92頁
文件大?。?/td> 1672K
代理商: MSP430F2002IRSA
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491H
– AUGUST 2005 – REVISED AUGUST 2011
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the
CPU goes into LPM4 immediately after power-up.
Table 7. Interrupt Sources
SYSTEM
INTERRUPT SOURCE
INTERRUPT FLAG
WORD ADDRESS
PRIORITY
INTERRUPT
Power-up
PORIFG
External reset
RSTIFG
Watchdog Timer+
WDTIFG
Reset
0FFFEh
31, highest
Flash key violation
KEYV
PC out-of-range(1)
See (2)
NMI
NMIIFG
(non)-maskable,
Oscillator fault
OFIFG
(non)-maskable,
0FFFCh
30
Flash memory access violation
ACCVIFG(2)(3)
(non)-maskable
0FFFAh
29
0FFF8h
28
Comparator_A+ (MSP430F20x1)
CAIFG(4)
maskable
0FFF6h
27
Watchdog Timer+
WDTIFG
maskable
0FFF4h
26
Timer_A2
TACCR0 CCIFG(4)
maskable
0FFF2h
25
Timer_A2
TACCR1 CCIFG.TAIFG(2)(4)
maskable
0FFF0h
24
0FFEEh
23
0FFECh
22
ADC10 (MSP430F20x2)
ADC10IFG(4)
maskable
0FFEAh
21
SD16CCTL0 SD16OVIFG,
SD16_A (MSP430F20x3)
maskable
SD16CCTL0 SD16IFG(2)(4)
USI
USIIFG, USISTTIFG(2)(4)
maskable
0FFE8h
20
(MSP430F20x2, MSP430F20x3)
I/O Port P2 (two flags)
P2IFG.6 to P2IFG.7(2)(4)
maskable
0FFE6h
19
I/O Port P1 (eight flags)
P1IFG.0 to P1IFG.7(2)(4)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
See (5)
0FFDEh to 0FFC0h
15 to 0, lowest
(1)
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
(2)
Multiple source flags
(3)
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4)
Interrupt flags are located in the module.
(5)
The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
Copyright
2005–2011, Texas Instruments Incorporated
13
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