參數(shù)資料
型號： MSP430A017IPNR
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PQFP80
封裝： GREEN, PLASTIC, QFP-80
文件頁數(shù)： 37/73頁
文件大?。?/td> 1185K
代理商： MSP430A017IPNR
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380A APRIL 2004 REVISED SEPTEMBER 2004
42
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit DAC, reference input specifications
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VeREF+
Reference input
DAC12IR=0, (see Notes 1 and 2)
2.2V/3V
AVCC/3 AVCC+0.2
V
VeREF+
Reference input
voltage range
DAC12IR=1, (see Notes 3 and 4)
2.2V/3V
AVcc
AVcc+0.2
V
DAC12_0 IR=DAC12_1 IR =0
2.2V/3V
20
M
DAC12_0 IR=1, DAC12_1 IR = 0
2.2V/3V
40
48
56
k
Ri(VREF+),
Reference input
DAC12_0 IR=0, DAC12_1 IR = 1
2.2V/3V
40
48
56
k
Ri(VREF+),
Ri(VeREF+)
Reference input
resistance
DAC12_0 IR=DAC12_1 IR =1
DAC12_0 SREFx = DAC12_1 SREFx
(see Note 5)
2.2V/3V
20
24
28
k
NOTES:
1. For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
2. The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC VE(O)] / [3*(1 + EG)].
3. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
4. The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC VE(O)] / (1 + EG).
5. When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1 (see Figure 25 and Figure 26)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
DAC12 on-
DAC12_xDAT = 800h,
DAC12AMPx=0
→ {2, 3, 4}
2.2V/3V
60
120
tON
DAC12 on-
time
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB
DAC12AMPx=0
→ {5, 6}
2.2V/3V
15
30
s
tON
time
ErrorV(O) < ±0.5 LSB
(see Note 1,Figure 25)
DAC12AMPx=0
→ 7
2.2V/3V
6
12
s
Settling
DAC12_xDAT =
DAC12AMPx=2
2.2V/3V
100
200
tS(FS)
Settling
time,full-scale
DAC12_xDAT =
80h
→ F7Fh→ 80h
DAC12AMPx=3,5
2.2V/3V
40
80
s
tS(FS)
time,full-scale
80h
→ F7Fh→ 80h
DAC12AMPx=4,6,7
2.2V/3V
15
30
s
Settling time,
DAC12_xDAT =
DAC12AMPx=2
2.2V/3V
5
tS(C-C)
Settling time,
code to code
DAC12_xDAT =
3F8h
→ 408h→ 3F8h
DAC12AMPx=3,5
2.2V/3V
2
s
tS(C-C)
code to code
3F8h
→ 408h→ 3F8h
BF8h
→ C08h→ BF8h
DAC12AMPx=4,6,7
2.2V/3V
1
s
DAC12_xDAT =
DAC12AMPx=2
2.2V/3V
0.05
0.12
SR
Slew Rate
DAC12_xDAT =
80h
→ F7Fh→ 80h
DAC12AMPx=3,5
2.2V/3V
0.35
0.7
V/
s
SR
Slew Rate
80h
→ F7Fh→ 80h
DAC12AMPx=4,6,7
2.2V/3V
1.5
2.7
V/
s
DAC12_xDAT =
DAC12AMPx=2
2.2V/3V
10
Glitch energy: full-scale
DAC12_xDAT =
80h
→ F7Fh→ 80h
DAC12AMPx=3,5
2.2V/3V
10
nV-s
Glitch energy: full-scale
80h
→ F7Fh→ 80h
DAC12AMPx=4,6,7
2.2V/3V
10
nV-s
NOTES:
1. RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 25.
2. Slew rate applies to output voltage steps >= 200mV.
RLoad
AVCC
CLoad = 100pF
2
DAC Output
RO/P(DAC12.x)
ILoad
Conversion 1
Conversion 2
VOUT
Conversion 3
Glitch
Energy
+/ 1/2 LSB
tsettleLH
tsettleHL
= 3 k
Figure 25. Settling Time and Glitch Energy Testing
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