參數(shù)資料
型號(hào)： MSP430A002IPMR
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PQFP64
封裝： GREEN, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 31/62頁(yè)
文件大小： 1007K
代理商： MSP430A002IPMR
MSP430x13x, MSP430x14x, MSP430x14x1
MIXED SIGNAL MICROCONTROLLER
SLAS272F JULY 2000 REVISED JUNE 2004
37
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, timing parameters
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
fADC12CLK
For specified performance of ADC12
linearity parameters
2.2V/
3V
0.45
5
6.3
MHz
fADC12OSC
Internal ADC12
oscillator
ADC12DIV=0,
fADC12CLK=fADC12OSC
2.2 V/
3V
3.7
6.3
MHz
tCONVERT
Conversion time
CVREF+ ≥ 5 F, Internal oscillator,
fADC12OSC = 3.7 MHz to 6.3 MHz
2.2 V/
3 V
2.06
3.51
s
tCONVERT
Conversion time
External fADC12CLK from ACLK, MCLK or SMCLK:
ADC12SSEL
≠ 0
13
×ADC12DIV×
1/fADC12CLK
s
tADC12ON
Turn on settling time of
the ADC
(see Note 1)
100
ns
tSample
Sampling time
RS = 400 , RI = 1000 ,
CI = 30 pF
3 V
1220
ns
tSample
Sampling time
S
I
CI = 30 pF
τ = [RS + RI] x CI;(see Note 2)
2.2 V
1400
ns
Not production tested, limits characterized
Not production tested, limits verified by design
NOTES:
1. The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
2. Approximately ten Tau (
τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance.
12-bit ADC, linearity parameters
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
EI
Integral linearity error
1.4 V
≤ (VeREF+ VREF/VeREF) min ≤ 1.6 V
2.2 V/3 V
±2
LSB
EI
Integral linearity error
1.6 V < (VeREF+ VREF/VeREF) min ≤ [V(AVCC)]
2.2 V/3 V
±1.7
LSB
ED
Differential linearity
error
(VeREF+ VREF/VeREF)min ≤ (VeREF+ VREF/VeREF),
CVREF+ = 10 F (tantalum) and 100 nF (ceramic)
2.2 V/3 V
±1
LSB
EO
Offset error
(VeREF+ VREF/VeREF)min ≤ (VeREF+ VREF/VeREF),
Internal impedance of source RS < 100 ,
CVREF+ = 10 F (tantalum) and 100 nF (ceramic)
2.2 V/3 V
±2
±4
LSB
EG
Gain error
(VeREF+ VREF/VeREF)min ≤ (VeREF+ VREF/VeREF),
CVREF+ = 10 F (tantalum) and 100 nF (ceramic)
2.2 V/3 V
±1.1
±2
LSB
ET
Total unadjusted
(VeREF+ VREF/VeREF)min ≤ (VeREF+ VREF/VeREF),
CVREF+ = 10 F (tantalum) and 100 nF (ceramic)
2.2 V/3 V
±2
±5
LSB
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