參數(shù)資料
型號(hào)： MSP3445G
廠商： Electronic Theatre Controls, Inc.
英文描述： MSP 34x5G Multistandard Sound Processor Family
中文描述： 中型34x5G多標(biāo)準(zhǔn)聲音處理器系列
文件頁(yè)數(shù)： 56/98頁(yè)
文件大?。?/td> 1541K
代理商： MSP3445G
MSP 34x5G
PRELIMINARY DATA SHEET
56
Micronas
4.6.2.4. Crystal Recommendations
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
General Crystal Recommendations
f
P
Crystal Parallel Resonance Fre-
quency at 12 pF Load Capacitance
18.432
MHz
R
R
Crystal Series Resistance
8
25
C
0
Crystal Shunt (Parallel) Capacitance
6.2
7.0
pF
C
L
External Load Capacitance
1)
XTAL_IN,
XTAL_OUT
PSDIP
P(L,M)QFPapprox. 3.3
approx. 1.5
pF
pF
Crystal Recommendations for Master-Slave Applications
(MSP-clock must perform synchronization to I
2
S clock)
f
TOL
Accuracy of Adjustment
20
+
20
ppm
D
TEM
Frequency Variation
versus Temperature
20
+
20
ppm
C
1
Motional (Dynamic) Capacitance
19
24
fF
f
CL
Required Open Loop Clock
Frequency (T
amb
= 25
°
C)
18.431
18.433
MHz
1)
External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop fre-
quency of the internal PLL and to stabilize the frequency in closed-loop operation. Due to different layouts, the
accurate capacitor value should be determined with the customer PCB. The suggested values (1.5...3.3 pF) are
figures based on experience and should serve as
“
start value
”
.
To adjust the capacitor value, reset the MSP and transfer only the following I
2
C-protocol:
<80 10 00 20 00 60>.
Measure the frequency at pin ADR_CL. Measurement at XTAL_IN/OUT pins is not possible. Change the
capacitor value until the frequency matches 18.432/3 = 6.144 MHz as closely as possible. The higher the
capacity, the lower the resulting clock frequency.
Note:
To minimize adjustment tolerances for all MSP-generations, it is strongly recommended to use the so-
called MSP-XTAL-REF ICs
(available in all packages)
for the capacitor adjustment. Since all MSP-XTAL-REF ICs
do have an AUD_CL_OUT-pin with the 18.432 MHz signal, this pin should be used for the capacitor adjustment
instead of the ADR_CL-pin. After the reset, no I
2
C-protocol should be transmitted. The AUD_CL_OUT-signal is
available at the following pins:
PLCC68
PSDIP64
PSDIP52
PQFP80
PLQFP64
PMQFP44
2)
pin 18
pin 1
pin 2
pin 74
pin 57
pin 8
2)
For the MSP-XTAL-REF IC, the PMQFP44 pin functionality of the D_CTR_I/O1-pin has been changed to
the Audio_Clock_Out signal
. If D_CTR_I/O1 is used in the customer application, this pin must be left open for
the adjustment procedure.
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