參數(shù)資料
型號： MSP3430
廠商： Electronic Theatre Controls, Inc.
英文描述： Multistandard Sound Processor Family
中文描述： 多標(biāo)準(zhǔn)聲音處理器系列
文件頁數(shù)： 81/101頁
文件大?。?/td> 752K
代理商： MSP3430
PRELIMINARY DATA SHEET
MSP 34x0G
Micronas
81
6. Appendix B: Manual/Compatibility Mode
To adapt the modes of the STANDARD SELECT regis-
ter to individual requirements and for reasons of
com-
patibility to the MSP 34x0D,
the MSP 34x0G offers
an Manual/Compatibility Mode, which provides sophis-
ticated programming of the MSP 34x0G.
Using the STANDARD SELECT register generally pro-
vides a more economic way to program the
MSP 34x0G and will result in optimal behavior.
There-
fore, it is not recommend to use the Manual/Com-
patibility mode.
In those cases, where the
MSP 34x0D is to be substituted by the MSP 34x0G,
the tips given in Section 6.10. on page 97 have to be
obeyed by the controller software.
6.1. Demodulator Write and Read Registers for Manual/Compatibility Mode
Table 6
–
1:
Demodulator Write Registers; Subaddress: 10
hex
; these registers are not readable!
Demodulator
Write Registers
Address
(hex)
MSP-
Version
Description
Reset
Mode
Page
AUTO_FM/AM
00 21
3410,
3450
1. MODUS[0]=1 (Automatic Sound Select):
Switching Level threshold of
Automatic Switching between NICAM and FM/AM in case of bad NICAM
reception
2. MODUS[0]=0 (Manual Mode):
Activation and configuration of Automatic
Switching between NICAM and FM/AM in case of bad NICAM reception
00 00
83
A2_Threshold
00 22
all
A2 Stereo Identification Threshold
00 19
hex
85
CM_Threshold
00 24
all
Carrier-Mute Threshold
00 2A
hex
85
AD_CV
00 BB
all
SIF-input selection, configuration of AGC, and Carrier-Mute Function
00 00
86
MODE_REG
00 83
3410,
3450
Controlling of MSP-Demodulator and Interface options. As soon as this
register is applied, the MSP 34x0G works in the
MSP 34x0D compatibility
mode.
Warning: In this mode, BTSC, EIA-J, and FM-Radio are disabled.
Only
MSP 34x0D features are available; the use of MODUS and STATUS register
is not allowed.
The MSP 34x0G is reset to the normal mode by first programming the
MODUS register followed by transmitting a valid standard code to the
STANDARD SELECTION register.
00 00
87
FIR1
FIR2
00 01
00 05
FIR1-filter coefficients channel 1 (6
8 bit)
FIR2-filter coefficients channel 2 (6
8 bit),
+
3
8 bit offset (total 72 bit)
00 00
89
DCO1_LO
DCO1_HI
DCO2_LO
DCO2_HI
00 93
00 9B
00 A3
00 AB
Increment channel 1 Low Part
Increment channel 1 High Part
Increment channel 2 Low Part
Increment channel 2 High Part
00 00
89
PLL_CAPS
00 1F
Not of interest for the customer
Switchable PLL capacitors to tune open-loop frequency
00 56
92
Note:
All registers except AUTO_FM/AM, A2_Threshold, and CM_Threshold are initialized during STANDARD SELECTION and are
automatically updated when Automatic Sound Select (MODUS[0]=1) is on.
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