參數(shù)資料
型號： MSM82C59A-2JS
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： PROGRAMMABLE INTERRUPT CONTROLLER
中文描述： 可編程中斷控制器
文件頁數(shù)： 25/28頁
文件大?。?/td> 186K
代理商： MSM82C59A-2JS
25/28
Semiconductor
MSM82C59A-2RS/GS/JS
Precautions for operation
Contents: In the case of a cascade edge trigger, the low level width (TILIH) of a slave INT signal
may be less than the low level width (TJLJH:100 ns min.) of a master IR input signal.
This occurs when an interruption request with high order priority is provided to the
slave unit before the INTA cycle ends. Fig.1 shows a system configuration, Fig.2 a bug
operation timing chart, and Fig.3 a normal operation timing chart. TILIH is not
specified.
MSM82C59A-2
Master
CPU
INTR
INTA
INTm
INT
INTA
IR
7
INTs
MSM82C59A-2
Slave
INTA
IR
1
s
IR
1
IR
2
s
IR
2
IR
7
m
INT
Fig. 1 System Configuration
IR
2S
IR
1S
INTA
INT
S
(IR
7
m)
INTm
TILIH (TJLJH) does not satisfy
the spec.
INT
S
is not accepted.
Fig. 2 Bug Operation Timing Chart
IR
2S
TILIH
(TJLJH)
IR
1S
INTA
INT
S
(IR
7
m)
INTm
Fig. 3 Normal Operation Timing Chart
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