參數(shù)資料
型號(hào)： MSM82C55A-2VJS
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 微控制器/微處理器
英文描述： 24 I/O, PIA-GENERAL PURPOSE, PQCC44
封裝： 0.650 INCH, 1.27 MM PITCH, PLASTIC, QFJ-44
文件頁數(shù)： 6/26頁
文件大?。?/td> 173K
代理商： MSM82C55A-2VJS
14/26
Semiconductor
MSM82C55A-2RS/GS/VJS
OBF (Output buffer full flag output)
This signal when turned to low level indicates that data is written to the specified port upon
receipt of the WR signal from the CPU. This signal turns to low level at the rising edge of
the WR and high level at the falling edge of the ACK.
ACK (Acknowledge input)
This signal when turned to low level indicates that the terminal has received data.
INTR (Interrupt request output)
This is the signal used to interrupt the CPU when a terminal receives data from the CPU via
the MSM82C55A-5. It indicates the occurrence of the interrupt in high level only when the
internal INTE flip-flop is set. This signal turns to high level at the rising edge of the ACK
(OBF = 1 at this time) and low level at the falling edge of WR when the INTE B is set.
INTE A of group A is set when the bit for PC6 is set, while INTE B of group B is set when the
bit for PC2 is set.
Mode 1 Input
(Group A)
PA7
PA0
-
8
INTEA
PC4
PC5
STBA
IBFA
PC3
INTRA
RD
(Group B)
PB7
PB0
-
INTEB
PC2
PC1
STBB
IBFB
PC0
INTRB
RD
8
Note:
Although belonging to group B, PC3 operates as the control signal of
group A functionally.
Mode 1 Output
(Group A)
PA7
PA0
-
8
INTEA
PC7
PC6
OBFA
ACKA
PC3
INTRA
WR
(Group B)
PB7
PB0
-
8
INTEB
PC1
PC2
OBFB
ACKB
PC0
INTRB
WR
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