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參數(shù)資料
| 型號： | MSM81C55-5GS |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 2048-Bit CMOS STATIC RAM WITH I/O PORTS AND TIMER |
| 中文描述： | 2048位CMOS靜態(tài)RAM與I / O端口和定時器 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 156K |
| 代理商： | MSM81C55-5GS |
13/19
Semiconductor
MSM81C55-5RS/GS/JS
M
2
0
0
M
1
0
1
Outputs a low-level signal in the latter half (Note 1) of a count period.
Outputs a low-level signal in the latter half of a count period, automatically
loads the programmed count length, and restarts counting when the TC
value is reached.
Outputs a pulse when the TC value is reached.
Outputs a pulse each time the preset TC value is reached, automatically
loads the programmed count length, and restarts from the beginning.
1
1
0
1
Notes: 1. When counting an asymmetrical value such as (9), a high level is output during
the first period of five,and a low level is output during the second period of four.
2. If an internal counter of the MSM81C55-5 receives a reset signal, count operation
stops but the counter is not set to a specific initial value or output mode. When
restarting count operation after reset, the START command must be executed
again through the C/S register.
Note that while the counter is counting, you may load a new count and mode into the CLR.
Before the new count and mode will be used by the counter, you must issue a START
command to the counter. Please note the timer circuit on the MSM81C55-5 is designed to
be a square-wave timer, not a event counter. To achieve this, it counts down by twos twice
in completing one cycle. Thus, its registers do not contain values directly representing the
number of TIMER IN pulse received. After the timer has started counting down, the values
residing in the count registers can be used to calculate the actual number of TIMER IN pulse
required to complete the timer cycle if desired. To obtain the remaining count, perform the
following operations in order.
1.
2.
3.
4.
5.
STOP the counter
Read in the 16-bit value from the count registers.
Reset the upper two mode bits
Reset the carry and rotate right one position all 16 bits through carry
If carry is set, add 1/2 of the full original count (1/2 full count-1 if full count is odd).
Note: If you started with an odd count and you read the count registers before the third
count
pulse occurs, you will not be able to recognize whether one or two
counts have
occurred. Regardless of this, the MSM81C55-
5 always counts out the right number of pulses
TIMER OUT
TIMER-IN
in generating the
5
5
3
4
2
(TC)
5
5
5
3
4
2
(TC)
5
3
4
Start
Start
n=5
(Square Wave)
(Pulse)
n=4
(Square Wave)
(Pulse)
WR
TIMER-OUT
TIMER-OUT
WR
TIMER-OUT
TIMER-OUT
Note:
n is the value set in the CLR. Figures in the diagram refer to counter values
相關PDF資料 |
PDF描述 |
|---|---|
| MSM81C55-5JS | 2048-Bit CMOS STATIC RAM WITH I/O PORTS AND TIMER |
| MSM81C55-5RS | 2048-Bit CMOS STATIC RAM WITH I/O PORTS AND TIMER |
| MSM81C55-5 | 2k-bit Static RAM (256 bytes) With Parallel I/O Ports And A Timer(擴展CPU的RAM、定時器和I/O口) |
| MSM82C37B-5GS | PROGRAMMABLE DMA CONTROLLER |
| MSM82C43 | INPUT/OUTPUT PORT EXPANDER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MSM81C55-5JS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:2048-Bit CMOS STATIC RAM WITH I/O PORTS AND TIMER |
| MSM81C55-5RS | 制造商:ROHM Semiconductor 功能描述: 制造商:OK International 功能描述: |
| MSM82C37B-5GS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:PROGRAMMABLE DMA CONTROLLER |
| MSM82C37B-5JS | 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHZ, DMA CONTROLLER, PQCC44 |
| MSM82C37B-5RS | 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PDIP40 |
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