參數(shù)資料
型號(hào)： MSM80C154S
廠商： OKI SEMICONDUCTOR CO., LTD.
元件分類(lèi)： 8位微控制器
英文描述： CMOS 8-bit Microcontroller
中文描述： 的CMOS 8位微控制器
文件頁(yè)數(shù)： 31/40頁(yè)
文件大?。?/td> 257K
代理商： MSM80C154S
31/40
MSM80C154S/83C154S
Semiconductor
(3) External data memory access AC characteristics
*1 The variable check is from 0 to 24 MHz when the external check is used.
*2 For 2.2
￡
V
CC
<4 V
Parameter
Symbol
Unit
Min.
41.7
2t
CLCL
-40
Max.
1000
—
1 to 24 MHz
Variable clock from
ns
ns
t
CLCL
t
LHLL
XTAL1, XTAL2 Oscillator Cycle
ALE Signal Width
Address Setup Time
(to ALE Falling Edge)
Address Hold Time
(from ALE Falling Edge)
RD
Signal Width
WR
Signal Width
RAM Data Read Time
(from
RD
Signal Falling Edge)
RAM Data Read Hold Time
(from
RD
Signal Rising Edge)
Data Bus Floating Time
(from
RD
Signal Rising Edge)
RAM Data Read Time
(from ALE Signal Falling Edge)
RAM Data Read Time
(from Address Output)
RD
/
WR
Output Time from ALE
Falling Edge
RD
/
WR
Output Time from Address
Output
WR
Output Time from Data Output
Time from Data to
WR
Rising Edge
Data Hold Time
(from
WR
Rising Edge)
Time from to Address Float
RD
Output
Time from
RD
/
WR
Rising Edge to
ALE Rising Edge
1t
CLCL
-15
—
ns
t
AVLL
1t
CLCL
-35
—
ns
t
LLAX
6t
CLCL
-100
6t
CLCL
-100
—
—
ns
ns
t
RLRL
t
WLWH
—
5t
CLCL
-105
ns
t
RLDV
0
—
ns
t
RHDX
—
2t
CLCL
-70
ns
t
RHDZ
—
8t
CLCL
-100
ns
t
LLDV
—
9t
CLCL
-105
ns
t
AVDV
3t
CLCL
-40
3t
CLCL
-100
3t
CLCL
+40
ns
t
LLWL
4t
CLCL
-70
—
ns
t
AVWL
1t
CLCL
-40
7t
CLCL
-105
—
—
ns
ns
t
QVWX
t
QVWH
2t
CLCL
-50
—
ns
t
WHQX
0
—
ns
t
RLAZ
1t
CLCL
-30
1t
CLCL
+40
1t
CLCL
+100
ns
t
WHLH
*1
*2
*2
V
CC
=2.2 to 6.0V, V
SS
=0V, Ta=–40°C to +85°C
PORT 0, ALE, and
PSEN
connected with 100pF load, other connected with 80pF load
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