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參數(shù)資料
| 型號： | MSM66G101VS |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 10 MHz, MICROCONTROLLER, CDIP64 |
| 封裝： | 0.750 INCH, 1.78 MM PITCH, CERAMIC, PIGGY BACK, DIP-64 |
| 文件頁數(shù)： | 27/28頁 |
| 文件大?。?/td> | 574K |
| 代理商： | MSM66G101VS |
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Semiconductor
MSM66101
RESOUT
Outputs 'H' level when the CPU is in RESET status.
Reset to 'L' level in some programs.
ALE
Address Latch Enable:
PSEN
Program Store Enable:
RD
Output strobe activated during a bus read cycle.
Used to enable data on to the bus from the external data memory.
WR
Output strobe during a bus write cycle.
Used as write strobe to external data memory.
I
READY
Used when the CPU accesses low speed peripherals.
EA
Normally set to 'H' level.
If set to 'L' level, the CPU fetches the code from external program memory.
FLT
If FLT is 'H' level, ALE, WR, RD, PSEN are set to 'H' level when reset.
If FLT is set to 'L', ALE, WR, RD, PSEN are set to floating level when reset.
RES
RESET input pin.
OSC1
NMI
Nonmaskable interrupt input pin (falling edge)
VREF
Reference voltage input pin for A/D converter.
AGND
Ground for A/D converter.
VDD
System power supply.
GND
Ground.
Type
Description
Symbol
O
I
O
I
The timing pulse to latch the lower 8 bits of the address
output from port 0 when the CPU accesses the external
memory.
The strobe pulse to fetch to external program
memory.
OSC0
Clock oscillation pins
I
PIN DESCRIPTIONS (Continued)
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