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| 型號(hào)： | MSM66587ATS-K |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-100 |
| 文件頁(yè)數(shù)： | 258/269頁(yè) |
| 文件大?。?/td> | 1378K |
| 代理商： | MSM66587ATS-K |
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4
MSM66587 Family User's Manual
Chapter 4 CPU Control Functions
(2) STOP Mode
The device will enter STOP mode when n5H followed by nAH (n = 0-FH) are written to STPACP
to set (1) the Stop Code Acceptor, and then STP (bit 0) of SBYCON is set (1). The Stop Code
Acceptor will be reset (0) at the same time stop mode is entered.
STOP mode stops the oscillation clock, so TBC, timers, the serial port, etc. will also stop.
However, the general 8-bit timer (GTMC) will operate if an external clock has been selected.
The valid edge specification for the external clock will be disabled, so it will operate on the
falling edge.
The clock supply to the CPU will also stop, so instructions will not be executed. Execution will
stop at the instruction after the instruction that set ("1") STP (bit 0) in SBYCON.
STOP mode will be released when either an interrupt or reset by RES input occurs. The edge
specification for external interrupts (INT0-INT3) is disabled and the "L" level is enabled.
When a non-maskable interrupt occurs in STOP mode, STOP mode will be released
unconditionally and the CPU will execute the non-maskable interrupt process.
When a maskable interrupt occurs in STOP mode, STOP mode will be released when both its
Interrupt Request Flag (IRQ bit) and Interrupt Enable Flag (IE) are set ("1").
If the Master Interrupt Enable Flag (MIE of the PSW) has been set ("1"), then after STOP mode
is released the CPU will execute the maskable interrupt process for the interrupt. If it has been
reset ("0"), then the CPU will start execution at the instruction after the instruction that set
STOP mode (set the STP bit of SBYCON).
If STOP mode is set during an NMI routine and then released by an interrupt, execution after
release will start at the instruction after the instruction that set STOP mode. Also, if interrupt
priority has been set (MIP = 1) and STOP mode is entered from within a high-priority interrupt
routine, then STOP mode can be released by interrupt requests of lower priority but the lower
priority interrupt process will not be executed even though MIE is 1. Instead the CPU will start
execution at the instruction after the instruction that set STOP mode.
Figure 4-2 shows STOP mode timing.
When STOP mode is released by RES pin input, the CPU will perform its reset processing.
When releasing by RES pin input, apply a low level on the RES pin until the oscillation clock
is stable.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MSM66587TS-K | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:Built-in 16 bit PWM and 8 bit A/D Converter, High-speed High-preformance 16 bit Microcontroller |
| MSM66589 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:OLMS-66K Series CMOS 16-Bit Microcontroller |
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| MSM6658A | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:Internal Mask ROM Voice Synthesis IC, Internal One-Time-Programmable OTP ROM Voice Synthesis IC, External ROM Drive Voice Synthesis IC |
| MSM6658A-XXX | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:Internal Mask ROM Voice Synthesis IC, Internal One-Time-Programmable OTP ROM Voice Synthesis IC, External ROM Drive Voice Synthesis IC |
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