12-36
MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
Synchronous mode
[Master mode]
Figure 12-16 shows the timing diagram of operation during master mode reception.
The clock pulse from the baud rate generator (timer 4 for SIO1 and timer 3 for SIO6) is
divided by 4 to generate the external output clock. The 3rd pulse of the 1/4 divider (value
2 of the baud rate (1/4) counter in figure 12-16) becomes the sampling clock for the receive
data input pin (RXDn). The 4th pulse (value 3 of the baud rate (1/4) counter in figure 12-
16) becomes the receive shift clock.
In synchronization with the receive shift clock, the reception circuit controls reception of the
receive data.
The falling edge of the receive shift clock immediately after SRnREN (bit 7) of SRnCON is
set to "1" triggers the reception operation to start and the external output clock is output from
the receive clock I/O pin (RXCn). At the next receive shift clock, receive data that was
sampled at the prior sampling clock is shifted into the receive shift register.
At the falling edge of the external output clock, the transmit side transmits data. That data
is shifted into the receive side at the falling edge of the transmit shift clock. Receive data
is sampled only once. Thereafter, data reception continues as specified by SRnCON. After
the last receive shift clock is output, the contents of the receive shift register are transferred
to SnBUF, and a receive complete signal is generated in synchronization with M1S1, the
signal that indicates the beginning of an instruction. At this time, an overrun error will be
generated if the previously received data has not been read (the previously received data
will be overwritten).
Finally, SRnREN of SRnCON is automatically cleared to "0" to complete the reception
series.
[Slave mode]
Figure 12-17 shows the timing diagram of operation during slave mode reception.
In the slave mode, the receive clock is input externally (from the receive clock I/O pin
(RXCn)). This external input clock is detected with the edge of CPU clock to generate the
receive shift clock.
In synchronization with the receive shift clock that has been generated, the reception circuit
controls receiving the receive data.
Reception operation is triggered to begin when SRnREN (bit 7) of SRnCON is set to "1" and
the external input clock is input to the receive clock I/O pin (RXCn).
While the external input clock is at a Low level, the value of the receive data input pin (RXDn)
is sampled. The sampled receive data is shifted into the receive shift register at the next
receive shift clock. Thereafter, data reception continues as specified by SRnCON. After
the last receive data is shifted in, the contents of the receive shift register are transferred
to SnBUF, and a receive complete signal is generated in synchronization with M1S1, the
signal that indicates the beginning of an instruction. At this time, an overrun error will be
generated if the previously received data has not been read (the previously received data
will be overwritten). This completes a one frame reception.
In the slave mode, SRnREN is not automatically cleared to "0" after completing the
reception. If the receive shift clock continues to be input, the receive operation will restart.