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MSM66577 Family User's Manual
Chapter 12 Serial Port Functions
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Serial input FIFO data register (SIN5)
The serial input FIFO data register (SIN5) is used to read 8-bit serial data received from the
SIO pin. Since SIN5 is read-only, do not attempt to write to this register.
When 1 byte of received data has been gathered in the shift register, it is automatically
loaded into the FIFO register. When transfer of the specified number of bytes is complete,
an interrupt is generated. After the interrupt is generated, by reading SIN5, data can be read
in order from the earliest received data. Because incorrect transmission or reception will
occur if SIN5 is read during serial transmission or reception, do not attempt to read SIN5
while a transmission or reception is in progress.
When reset (
RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of SIN5 are undefined.
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Serial output FIFO data register (SOUT5)
The serial output FIFO data register (SOUT5) is used to write the 8-bit serial data to be
output from the SIOO5 pin. Since SOUT5 is write-only, do not attempt to read this register.
After data written to the SOUT5 register has been stored in the FIFO register, the start of
transmission or reception causes that data to be sequentially loaded into a shift register.
Because incorrect transmission or reception will occur if SOUT5 is written to during serial
transmission or reception, do not attempt to write to SOUT5 while a transmission or
reception is in progress.
When reset (
RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), the contents of SOUT5 are undefined.
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FIFO mode control register (FIFOMOD)
The FIFO mode control register (FIFOMOD) is a 2-bit register that specifies the mode of
combined SIO4 and SIO5 usage. However, write operations to bits 2 through 7 are invalid.
If bits 2 through 7 are read, a value of "1" will always be obtained.
When reset (
RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), FIFOMOD becomes FCH.
Bits 0 and 1 (FMOD0, FMOD1) select the mode of combined SIO4 and SIO5 usage.
Change these flags when neither SIO4 nor SIO5 is transferring data.
1) A mode
This mode operates SIO4 and SIO5 independently.
2) B mode
This mode alternates usage of SIO4 and SIO5 through the SIO4 port interface to
consecutively transfer multiple bytes of data without limitation due to the number of FIFO
stages. In this mode, operation of only master mode transmission and reception is possible.
In this mode, while a transfer is in progress for one SIO, even if the TEN flag of the other
SIO is set, that SIO's transfer will wait until the first SIO transfer is completed. After the first
SIO transfer is completed, the other SIO transfer will automatically start. This provides for
uninterrupted transfer.