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參數(shù)資料
| 型號： | MSM6568A |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | Dot Matrix LCD Controller(點矩陣LCD控制器) |
| 中文描述： | 點陣LCD控制器（點矩陣液晶顯示控制器） |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 64K |
| 代理商： | MSM6568A |
7/8
MSM6568A
Semiconductor
FUNCTIONAL DESCRIPTION
Pin Functional Description
IO
1
, IO
80
, IO
81
, IO
160
Data input/output pins for the two 80-bit bidirectional shift registers.
SHL
Input pin to select the shift direction of the two 80-bit bidirectional registers.
Table 1 shows the relations between the SHL pin and the IO
1
, IO
80
, IO
81
, IO
160
pins.
CP
Clock pulse input pin for the two 80-bit bidirectional shift registers.
Scan data shifts at the falling edge of a clock pulse.
DF
Signal input pin to synchronize with AC current for LCD driving waveforms.
Normally an inverted frame signal is input to this pin.
V
DDL
, V
DDR
, V
SSL
, V
SSR
Power supply pins.
Normal operating conditions are V
DDR
=V
DDL
=2.7 to 5.5V, V
SSR
=V
SSL
=0V.
DISPOFF
Input pin to control the O
1
to O
160
outputs. During input of "L" level, V
1
levels are output from
O
1
to O
160
.
V
1L
, V
1R
, V
2L
, V
2R
, V
5L
, V
5R
, V
EEL
, V
EER
Bias voltage input pins for LCD driving. Voltages must be input to all these pins.
O
1
to O
160
4-level driver output pins corresponding to each bit of the shift registers.
The V
1
, V
2
, V
5
, or V
EE
level is selected and output based on the combination of shift register data
and a DF signal.
Table 2 shows the relations between the scan data and the LCD driving outputs.
Table 1
Table 2
Scan data
H
L
LCD driving output
Select levels (V
1
, V
EE
)
Non-select levels (V
2
, V
5
)
SHL Shift direction IO
1
, IO
81
/ IO
80
, IO
160
I/O
Input
IO
1
and IO
81
are data input pins for the shift register.
Data is input to these pins in synchronization with clocks
and is output from IO
80
and IO
160
with delay by the number
(80) of shift register bits in synchronization with clocks.
IO
80
and IO
160
are data input pins for the shift register.
Data is input to these pins in synchronization with clocks
and is output from IO
1
and IO
81
with delay by the number
(80) of shift register bits in synchronization with clocks.
IO
1
, IO
81
Input
IO
80
, IO
160
Output
IO
80
, IO
160
Input
IO
1
, IO
81
Output
O
1
O
80
O
81
O
160
O
80
O
1
O
160
O
81
L
H
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