參數(shù)資料
型號(hào)： MSM6562B-xx
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： DOT MATRIX LCD CONTROLLER DRIVER
中文描述： 點(diǎn)陣LCD控制器驅(qū)動(dòng)
文件頁(yè)數(shù)： 29/50頁(yè)
文件大?。?/td> 496K
代理商： MSM6562B-XX
Semiconductor
MSM6562B-xx
29/50
12. Instruction Code
Instruction code table
Code
Instruction
Display clear
RS1RS0R/WDB7DB6DB5DB4DB3DB2DB1DB0
1
0
0
0
0
0
0
0
0
0
1
Description
Execution Time
CP
=
OSC
=250kHz
After all display are cleared,
address counter for DD RAM is
set to "00".
Address counter for DD RAM is set
to "00". The shifted display returns
to the position before shift. The
contents of the DD RAM are not
changed.
1
0
0
0
0
0
0
0
0
1
]
Cursor home
1.64ms
1.64ms
1
0
0
0
0
0
0
0
1
I/D
S
Entry mode setting
Direction of the cursor move and
whether display is shifted are set.
Upon data write or read, the cursor
and the display will actually be
moved and shifted.
40
m
s
Function setting
1
0
0
0
0
1
8B/
4B
N
F
]
]
The interface data length (8B/4B),
the display line numbers (N)
and the character font (F) are set.
The address of the CG RAM is set
and then the CG RAM data is
specified for the data for
transmission and reception.
The address of the DD RAM is set
and then the DD RAM data is
specified for the data for
transmission and reception.
40
m
s
Cursor/display shift
1
0
0
0
0
0
1 S/C R/L
]
]
The cursor and display are
shifted without changing the
contents of the DD RAM.
40
m
s
Display on/off control
1
0
0
0
0
0
0
1
D
C
B
The on/off of all display (D), the
on/off of the cursor (C) and the
blink (B) of the character at the
cursor position are set.
40
m
s
CG RAM address setting
1
0
0
0
1
ACG
40
m
s
The busy flag (BF) indicating that
the internal circuits are operating
and the contents of address counter
are read out.
DD RAM address setting
1
0
0
1
ADD
40
m
s
Busy flag/address read
1
0
1
BF
ADC
1
m
s
Data is written into the DD RAM
or CG RAM
1
1
0
WRITE DATA
Data is read out from the DD RAM
or CG RAM.
1
1
1
READ DATA
The data for contrast adjustment
is written.
0
0
0
0
WRITE CONTRAST
DATA
The data for contrast adjustment
is read.
Contrast adjusting data
read
0
0
1
0
0
0
1
0
Contrast adjusting data
write
CG RAM/DD RAM data
read
CG RAM/DD RAM data
write
40
m
s
40
m
s
40
m
s
40
m
s
READ CONTRAST
DATA
I/D=1
S=1
S/C=1
R/L=1
8B/4B=1
N=1
F=1
BF=1
:
:
:
:
:
:
:
:
Increment
Always involves di, I/D=0
Shift of display
Shift to the right
8 bits
2 lines
5
￥
10-dots
Engaged in
internal operation
, S/C=0
, R/L=0
, 8B/4B=0
, N=0
, F=0
, BF=0
:
:
:
:
:
:
:
Decrement
Shift of cursor
Shift to the left
4 bits
1 line
5
￥
7-dots
Instruction
acceptable
DD RAM
CG RAM
ACG
ADD
ADC
:
:
:
:
:
Display data RAM
Character generator RAM
CG RAM address
DD RAM address,
corresponding to the
cursor address
Address counter, used for
both DD RAM and CG
RAM
When the frequency
is changed, the
execution time is
also changed.
(Example)
When
CP
or
OSC
=270kHz,
40μs
￥
270
= 37μs
]
: Don't Care
250
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