參數(shù)資料
型號： MSM6542-03RS
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 時鐘/數(shù)據(jù)恢復及定時提取
英文描述： 0 TIMER(S), REAL TIME CLOCK, PDIP24
封裝： 0.600 INCH, PLASTIC, DIP-24
文件頁數(shù)： 11/54頁
文件大?。?/td> 406K
代理商： MSM6542-03RS
Semiconductor
MSM6542-01/02/03
86
b)
MASK
2 (D1)
This bit controls the alarm output each time the contents of the clock counter match the date
and time for which an alarm is set. When the bit is 0, an alarm is output from the
INTERRUPT OUT pin for the MSM6542-01/02 or the ALARM OUT pin for the MSM6542-
3. When the bit is 1, alarm output is disabled.
The relationships between causes of alarm output and the status of the MASK
2 bit are shown
below. (For the MSM6542-01/02, data resulting from the OR-ing of periodic output and
alarm output is output to the INTERRUPT OUT pin. For convenience, however, periodic
output is ignored in the following description.)
i)
In the alarm interrupt mode (when the IT/PLS
2 bit is 1)
The open status is entered when the IRQ FLAG2
is read. (*1)
A match for an alarm is not found
because the MASK2 bit is 1.
Open
Low level
Match for an alarm
"0"
"1"
INTERRUPT OUT (-01, -02)
ALARM OUT (-03)
MASK2 bit
When the IRQ FLAG2 is read during masking,
IRQ FLAG2 is not cleared. (*2)
*1
When DP = 1, the open state is not entered until a certain period
passes after an interrupt is generated. (See the description of the C
E
register.)
*2
However, when DP = 1, if the IRQ FLAG
2 bit is read out within
122
s after an interrupt is generated, it is cleared after 122s from the
generation of the interrupt.
ii)
In the alarm pulse output mode (when the IT/PLS
2 bit is 0)
When the IRQ FLAG2 bit is set at 0, the open state is
entered without having to wait for automatic
restration
The low level is not output
because the MASK2 bit is 1.
Open
Low level
Match for an alarm
"0"
"1"
MASK2 bit
Automatic restoration
INTERRUPT OUT
(-01, -02)
ALARM OUT
(-03)
"1"
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