參數(shù)資料
型號(hào)： MSM62X42B
廠(chǎng)商： OKI SEMICONDUCTOR CO., LTD.
英文描述： Real Time Clock IC With Built-In Crystal(具有內(nèi)置晶振的實(shí)時(shí)時(shí)鐘電路)
中文描述： 實(shí)時(shí)時(shí)鐘芯片，配有水晶（具有內(nèi)置晶振的實(shí)時(shí)時(shí)鐘電路）
文件頁(yè)數(shù)： 15/27頁(yè)
文件大?。?/td> 204K
代理商： MSM62X42B
Semiconductor
MSM62X42B
55
"1"
"0"
"0"
"1"
MASK BIT
STD.P
OUTPUT
OUTPUT DOES NOT OCCUR
AT LOW LEVEL BECAUSE
MASK BIT IS "1"
OPEN
LOW LEVEL
OUTPUT TIMING
AUTOMATIC RETURN
(When “0” is written to IRQ FLAG bit, at that time, STD.P
output becomes open without awaiting automatic return.)
IN TRT/STND BIT = "0"
b) ITRPT/STND (D
1
) (INTERRUPT/STANDARD PULSE)
This is a bit which gives the meaning for STD.P output. When this bit="1", the request for
interrupt is outputted at the STD.P output and when this bit="0", a fixed cycle waveform with
a low-level pulse width of 7.8125ms is present at the STD.P output. However, at this time,
the MASK bit must equal 0, while the period in either modes is determined by t
0
(D
2
) and
t
1
(D
3
) of register C
E
.
c) t
0
(D
2
), t
1
(D
2
) (time 0, 1)
When ITRPT/STND bit="1", this bit determines the interrupt period. When ITRPT/
STND bit="0", this bit determines the period of fixed timing waveform. The periods are
shown in the table below.
t
1
0
0
1
1
t
0
0
1
0
1
Period
1/64 second
1 second
1 minute
1 hour
Duty CYCLE of "L" level when
INRPT/STND bit is "0".
1/2
1/128
1/7680
1/460800
The timing of the STD.P output designated by t
1
and t
2
occurs at the moment that a carry
occurs to a clock digit.
PM12:00
PM1:00
(EXAMPLE) WHEN t
1
= 1, t
0
= 1 and MASK = 0
WHEN ITRPT/STND
BIT is "1"
STD.P OUTPUT
WHEN ITRPT/STND
BIT is "0"
OPEN
LOW LEVEL
OPEN
LOW LEVEL
The special counter is not included for t
1
and t
0
.
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