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參數(shù)資料
| 型號： | MSM6255GS-BK |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 顯示控制器 |
| 英文描述： | 128 X 256 CHARACTERS DOT MAT LCD DSPL CTLR, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 18/39頁 |
| 文件大?。?/td> | 477K |
| 代理商： | MSM6255GS-BK |
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MSM6255
Semiconductor
25/39
– Relation Between Reference Clock (fs) and External Clock
fs
DIV
XT
(
DIV = 1)
fs
T
Q
fs functions as a dot clock in LCDC and the dot counter inside the IC is counted up at the trailing
edge of fs.
The dot counter operates as a N-ary counter on a basis of HP and generates the character clocks
(CHf).
(Refer to the time charts Fig. 7 - 9 and Fig. 14.)
– Access to the Display RAM
In writing/reading the data to/from the display RAM, DIEN should be low level. By setting
DIEN signal at low level, the address from the CPU are output from MA0 - MA15, and this
enables the access to the display RAM.
There are three methods of accessing display RAM from the CPU.
(1) Direct access from CPU
Display RAM is accessed directly from the CPU, irrespective of the condition of MSM6255
(refresh cycle or not).
In this method, the RAM address changes to the CPU address when the display is on the
screen. So, frequent access to the RAM causes flickering on the screen.
(2) Access while BUSY signal is high
BUSY signal indicates the period when the data transfer stops, and BUSY signal is set high
when the data transfer stops. The period when BUSY signal is high corresponds to that of
seven characters’. If display RAM is accesed during this period (when BUSY is high), the
display on the screen does not flicker.
Note: This method is effective when the size of screen is small. In the case of big size
screen, 640 x 200 dots, 1character needs approx. 1.6ms. So, in this case, the period
when BUSY is at high level is 11.2ms, which is impossible to write or read a lot of
data.
(3) Synchronized access (only for operating the IC by external clock)
Refresh cycle and CPU cycle are alternately performed. So, there is not flickering on the
screen and there is no need to sense the BUSY signal.
When using this method, however, some external circuitry is necessary. The timing chart
of this method is described in the Figure 10 below.
相關PDF資料 |
PDF描述 |
|---|---|
| MSM6255GS-K | 128 X 256 CHARACTERS DOT MAT LCD DSPL CTLR, PQFP80 |
| MSM62725 | 8-BIT, MROM, 5 MHz, MICROCONTROLLER |
| MSM62X42BGS-1K | 1 TIMER(S), REAL TIME CLOCK, PDSO24 |
| MSM62X42BRS | 1 TIMER(S), REAL TIME CLOCK, PDIP18 |
| MSM62X42BGS-1K | REAL TIME CLOCK, PDSO24 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MSM6255GSK | 制造商:ROHM Semiconductor 功能描述: |
| MSM6262 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:DOT MATRIX LCD CONTROLLER WITH 48-DOT COMMON DRIVER |
| MSM6262-01 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:DOT MATRIX LCD CONTROLLER WITH 48 DOT COMMON DRIVER |
| MSM6262-XX | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:DOT MATRIX LCD CONTROLLER WITH 48-DOT COMMON DRIVER |
| MSM6295 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:4-CHANNEL MIXING ADPCM VOICE SYNTEHSIS LSI |
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