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參數(shù)資料
| 型號： | MSM6242BRS |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 時鐘/數(shù)據(jù)恢復及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP18 |
| 封裝： | 0.300 INCH, 2.54 MM PITCH, PLASTIC, DIP-18 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 293K |
| 代理商： | MSM6242BRS |
OKI Semiconductor
MSM6242B
15/23
FEDL6242B-02
TYPICAL APPLICATION INTERFACE WITH MSM6242B AND
MICROCONTROLLERS
D3
D2
D1
D0
A3
A2
A1
A0
CS0
ALE
RD
WR
AD3
AD2
AD1
AD0
A8 to A15
S1
S0
IO/M
ALE
RD
WR
8085
MSM6242B
Figure 15
DECODER
D3
D2
D1
D0
A3
A2
A1
A0
CS0
ALE
RD
WR
A/D
A8 to A15
S1
S0
IO/M
RD
WR
8085
MSM6242B
I/O MAPPED
D3
D2
D1
D0
A3
A2
A1
A0
RD
WR
A4 to A15
IORQ
MREQ
RD
WR
Z80
MSM6242B
DECODER
VDD
G1
Figure 16
MEMORY MAPPED
CS0
ALE
D3
D2
D1
D0
A3
A2
A1
A0
G2
D3
D2
D1
D0
A3
A2
A1
A0
RD
WR
ALE
RD
WR
MSC48
MSM6242B
DECODER
Figure 17
CS0
ALE
BUS3
BUS2
BUS1
BUS0
BUS 4-7
A8 to A12
DECODER
Note : If 8085 does not enter into the state of HALT or HOLD during CS1 = "H" of
MSM6242B, R1 and R2 are not required.
Note : It depends upon the switching
characterisrics decided by a X'tal used
for a Z80 that either of IORQ and MREQ
is used.
R1
R2
R1
R2
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