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參數(shù)資料
| 型號： | MSM5718B60 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 18-Megabit Low Latency RDRAM(18M位低待時RDRAM) |
| 中文描述： | 18兆位低延遲的RDRAM（1800萬位低待時的RDRAM） |
| 文件頁數(shù)： | 1/41頁 |
| 文件大?。?/td> | 233K |
| 代理商： | MSM5718B60 |
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Semiconductor
MSM5718B60
1/41
18-Megabit Low Latency RDRAM (2M
￥
9)
DESCRIPTION
The 18-Megabit Low Latency Rambus DRAM (RDRAM) is an extremely high-speed CMOS
DRAM organized as 2M words by 9 bits. It is capable of bursting up to 256 bytes of data at less than
2 nanoseconds per byte. The use of Rambus Signaling Logic (RSL) technology makes transfer rates
greater than 500 MHz achievable while using conventional system and board design methodologies.
Lower effective latency is attained by operating the dual 2KByte sense amplifiers as high speed
caches, and by using random access mode to facilitate large block transfers.
RDRAMs are general purpose high-performance memory devices suitable for use in a broad range
of applications including PC and consumer main memory, graphics, video, and any other
application where high-performance is required.
FEATURES
Rambus Interface:
Over 500 MB/sec peak transfer rate per RDRAM
Rambus Signaling Logic (RSL) interface
Synchronous protocol for fast block-oriented transfers
Direct connection to Rambus ASICs, MPUs, and Peripherals
15 active signals require just 32 total pins on the controller interface (including power)
3.3 V operation
Additional/multiple Rambus Channels provide an additional 500 MB/second band-width each
Dual 2KByte sense amplifiers may be operated as caches for low latency access
Random Access mode enables any burst order at full band width
Features for graphics include random-access mode, write-per-bit and mask-per-bit operations
Control and refresh logic entirely self-contained
On-chip registers for flexible addressing and timing
Available in horizontal surface mount plastic package (SHP32-P-1125-0.65-K)
Compatible with MSM5718B70
E2G1034-17-65
This version: Jan. 1998
Previous version: Jul. 1997
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