參數(shù)資料
型號(hào)： MSM54V32126A
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
中文描述： 131,072字× 32位動(dòng)態(tài)隨機(jī)存儲(chǔ)器：快速頁面模式型與江戶
文件頁數(shù)： 8/26頁
文件大?。?/td> 310K
代理商： MSM54V32126A
8/26
Semiconductor
MSM54V32126A
Notes:
1. An initial pause of 200
m
s is required after power-up followed by any 8
RAS
cycles
(Example :
RAS
only refresh) before proper device operation is achieved. In case of
using internal refresh counter, a minimum of 8
CAS
before
RAS
cycles instead of 8
RAS
cycles are required.
2. The AC characteristics assume at t
T
= 3 ns.
3. V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring timing of input signals.
Also, transition times are measured between V
IH
and V
IL
. Input levels at the AC testing
are 3.0 V/0 V.
4. Data outputs are measured with a load of 30 pF.
DOUT reference levels : V
OH
/V
OL
= 2.0 V/0.8 V.
5. t
REZ
(Max.), t
CEZ
(Max.), t
WEZ
(Max.) and t
OEZ
(Max.) define the time at which the
outputs achieve the open circuit condition and are not referenced to output voltage
levels. This parameter is sampled and not 100% tested.
6. Either t
RCH
or t
RRH
must be satisfied for a read cycle.
7. These parameters are referenced to
CAS
leading edge of early write cycles and to
WE
leading edge in
OE
controlled write cycles and read modify write cycles.
8. t
WCS
, t
RWD
, t
CWD
and t
AWD
are not restrictive operating parameters. They are included
in the data sheet as electrical characteristics only. If t
WCS
≥
t
WCS
(Min.), the cycle is an
early write cycle and the data out pin will remain open circuit throughout the entire
cycle; If t
RWD
≥
t
RWD
(Min.), t
CWD
≥
t
CWD
(Min.) and t
AWD
≥
t
AWD
(Min.), the cycle is
a read modify write cycle and the data out will contain data read from the selected cell:
If neither of the above sets of conditions is satisfied, the condition of the data out is
indeterminate.
9. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only: If t
RCD
is greater than the specified
t
RCD
(Max.) limit, then access time is controlled by t
CAC
.
10. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met. t
RAD
(Max.)
is specified as a reference point only: If t
RAD
is greater than the specified t
RAD
(Max.)
limit, then access time is controlled by t
AA
.
11. This is guaranteed by design. (t
DOH
= t
CAC
- output transition time) This parameter is
not 100% tested.
12. These parameters are determined by the earliest falling edge of
CAS1
,
CAS2
,
CAS3
, or
CAS4
.
13. These parameters are determined by the latest rising edge of
CAS1
,
CAS2
,
CAS3
, or
CAS4
.
14. t
CWL
should be satisfied by all
CAS
es.
15. t
CP
and t
CPT
are determined by the time that all
CAS
es are high.
相關(guān)PDF資料
PDF描述
MSM54V32126A-45GS-K 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
MSM54V32126A-45TS-K 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
MSM54V32126A-50GS-K 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
MSM54V32126A-50TS-K 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
MSM54V32126A-60GS-K 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
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