參數(shù)資料
型號： MSM54C865
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 65,536-Word X 8-Bit Multiport DRAM
中文描述： 65,536字× 8位多端口內(nèi)存
文件頁數(shù)： 41/44頁
文件大?。?/td> 479K
代理商： MSM54C865
MSM54C865
Semiconductor
41/44
Split Data Transfer and QSF
The MSM54C865 features a bidirectional split data transfer capability between the RAM and
SAM. During split data transfer operation, the serial register is split into two halves which can
be controlled independently. Split read or split write transfer operation can be performed to or
from one half of the serial register while serial data can be shifted into or out of the other half of
the serial register. The most significant column address location (A7C) is controlled internally to
determine which half of the serial register will be reloaded from the RAM. QSF is an output which
indicates which half of the serial register is in an active state. QSF changes state when the last SC
clock is applied to active split SAM.
Split Read Transfer Operation
Split read transfer consists of loading 128 words by 8 bits of data from a selected row of the split
RAM into the corresponding non-active split SAM register. Serial data can be shifted out from
of the other half of the split SAM register simultaneously. During split read transfer operation,
the RAM port input clocks do not have to be synchronized with the serial clock SC, thus
eliminating timing restrictions as in the case of real time read transfers. A split read transfer can
be performed after a delay of t
STS
, from the change of state of the QSF output, is satisfied.
Conventional (non-split) read transfer operation must be preceded by split read transfer
cycles.
Split Write Transfer Operation
Split write transfer consists of loading 128 words by 8 bits of data from the non-active split SAM
register into a selected row of the corresponding split RAM. Serial data can be shifted into the
other half of the split SAM register simultaneously. During split write transfer operation, the
RAM port input clocks do not have to be synchronized with the serial clock SC, thus allowing
for real time transfer. A split write transfer can be performed after a delay of t
STS
, from the change
of state of the QSF output, is satisfied.
A pseudo write transfer operation must precede split write transfer. The purpose of the pseudo
write transfer operation is to switch the SAM port from output mode to input mode and to set
the initial TAP location prior to split write transfer operation.
Transfer Operation Without
CAS
During all transfer cycles, the
CAS
input clock must be cycled, so that the column addresses
are latched at the falling edge of
CAS
, to set the SAM TAP location.
TAP Location in Split Transfer
1) In a split transfer operation, column address A0C through A6C must be latched at the falling
edge of
CAS
in order to set the TAP location in one of the split SAM registers. During a split
transfer, column address A7C is controlled internally and therefore it is ignored internally at the
falling edge of
CAS
. During a split transfer, it is not permissible to set the last address location
(A0C-A6C = 7F), in either the lower SAM or the upper SAM, as the TAP location.
相關(guān)PDF資料
PDF描述
MSM54C865-10 65,536-Word X 8-Bit Multiport DRAM
MSM54C865-10JS 65,536-Word X 8-Bit Multiport DRAM
MSM54C865-10ZS 65,536-Word X 8-Bit Multiport DRAM
MSM54C865-70 65,536-Word X 8-Bit Multiport DRAM
MSM54C865-70JS 65,536-Word X 8-Bit Multiport DRAM
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