參數(shù)資料
型號： MSM54C864-80JS
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 65,536-Word X 8-Bit Multiport DRAM
中文描述： 65,536字× 8位多端口內(nèi)存
文件頁數(shù)： 29/33頁
文件大小： 368K
代理商： MSM54C864-80JS
Semiconductor
MSM54C864
29/33
DATA TRANSFER OPERATION
The MSM54C864 features an internal data transfer capability between RAM and the SAM.
During a transfer cycle, 256 words by 8 bits of data can be loaded from RAM to SAM (Read
Transfer) or from SAM to RAM (Write Trasfer).
The MSM54C864 supports three types of transfer operations: Read transfer, Write Transfer and
pseudo write transfer. Data transfer operations between RAM and SAM are invoked by holding
the
DT
/
OE
signal “l(fā)ow” at the falling edge of
RAS
, the type of data transfer operation is
determined by the state of
CAS
,
WB
/
WE
and
SE
latched at the falling edge of
RAS
.
During data transfer operations, the SAM port is switched from input to output mode (Read
Transfer) or output to input mode (Write Transfer/Pseudo Write Trasfer).
During a data transfer cycle, the row A0-A7 select one of the 256 rows of the memory array to or
from which data will be transferred and the column address A0-A7 select one of the tap locations
in the serial register. The selected tap location is the start position in the SAM port from which
the first serial data will be read out during the subsequent serial read cycle or the start position
in the SAM port into which the first serial data will be written during the subsequent serial write
cycle.
Read Transfer Cycle
A read transfer consists of loading a selected row of data from the RAM array into the SAM
register. A read transfer is invoked by holding
CAS
“high”,
DT
/
OE
“l(fā)ow” and
WB
/
WE
“high”
at the falling edge of
RAS
. The row address selected at the falling edge of
RAS
determines the
RAM row to be transferred into the SAM.
The transfer cycle is completed at the rising edge of
DT
/
OE
. When the transfer is completed, the
SAM port is set into the output mode.
In a read/real time read transfer of a new row of data is completed at the rising edge of
DT
/
OE
and this data becomes valid on the SIO lines after the specified access time t
SCA
from the rising
edge of the subsequent serial clock (SC) cycle. The start address of the serial pointer of the SAM
is determined by the column address selected at the falling edge of
CAS
.
In a read transfer cycle preceded by a write transfer cycle, the SC clock must be held at a constant
V
IL
or V
IH
, after the SC high time has been satisfied. A rising edge of the SC clock must not occur
until after the specified delay t
TSD
from the rising edge of
DT
/
OE
.
In a real time read transfer cycle (which is perceded by another read transfer cycle), the previous
row data appears on the SIO lines until the
DT
/
OE
signal goes “high” and the serial access time
t
SCA
for the following serial clock is satisfied.
This feature allows for the first bit of the new row of data to appear on the serial output as soon
as the last bit of the previous row has been strobed without any timing loss. To make this
continuous data flow possible, the rising edge of
DT
/
OE
must be synchronized with
RAS
,
CAS
and the subsequent rising edge of SC (t
RTH
, t
CTH
, and t
TSL
/t
TSD
must be satisfied). The timing
restriction t
TSL
/t
TSD
are 5 ns min./10 ns min..
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