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參數(shù)資料
| 型號(hào)： | MSM54C864-80 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 65,536-Word X 8-Bit Multiport DRAM |
| 中文描述： | 65,536字× 8位多端口內(nèi)存 |
| 文件頁數(shù)： | 28/33頁 |
| 文件大小： | 368K |
| 代理商： | MSM54C864-80 |
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Semiconductor
MSM54C864
28/33
RAM PORT OPERATION
Fast Page Mode Cycle
Fast page mode allows data to be transferred into or out multiple column locations of the same
row by performing multiple
CAS
cycle during a single active
RAS
cycle.
During a fast page cycle, the
RAS
signal may be maintained active for a period up to 100
μ
seconds.
For the initial fast page mode access, the output data is valid after the specified access times from
RAS
,
CAS
, column address and
DT
/
OE
.
For all subsequent fast page mode read operations, the output data is valid after the specified
access times from
CAS
, column address and
DT
/
OE
. When the write-per-bit function is enabled,
the mask data latched at the falling edge of
RAS
is maintained throughout the fast page mode
write or Read-Modify-Write cycle.
RAS
-Only Refresh
The data is the DRAM requires periodic refreshing to prevent data loss. Refreshing is accomplished
by performing a memory cycle at each of the 256 rows in the DRAM array within the specified
4 ms refresh period.
Although any normal memory cycle will perform the refresh operation, this function is most
easily accomplished with “
RAS
-Only” cycle.
CAS
before
RAS
Refresh
The MSM54C864-JS/ZS also offers an internal-refresh function. When
CAS
is held “l(fā)ow” for a
specified period (t
CSR
) before
RAS
goes “l(fā)ow”, an internal refresh address counter and on-chip
refresh control clock generators are enabled and an internal refresh operation takes place.
When the refresh operation is completed, the internal refresh address counter is automatically
incremented in preparation for the next
CAS
-before-
RAS
cycle. For successive
CAS
-before-
RAS
refresh cycle,
CAS
can remain “l(fā)ow” while cycling
RAS
.
Hidden Refresh
A hidden refresh is a
CAS
-before-
RAS
refresh performed by holding
CAS
“l(fā)ow” from a previous
read cycle. This allows for the output data from the previous memory cycle to remain valid while
performing a refresh.
The internal refresh address counter provides the address and the refresh is accomplished by
cycling
RAS
after the specified
RAS
-precharge period.
Write-per-Bit Function
The Write-Per-Bit selectively controls the internal write-enable circuits of the RAM port. Write-
Per-Bit is enabled when
WB
/
WE
held “l(fā)ow” at the falling edge of
RAS
in a random write
operation. Also, at the falling edge of
RAS
, the mask data on the Wi/IOi pins are latched into a
write mask register. The write mask data must be presented at the Wi/IOi pins at every falling
edge of
RAS
. A “0” on any of the Wi/IOi pins will disable the corresponding write circuits and
new data will not be written into the RAM. A “1” on any of the Wi/IOi pins will enable the
corresponding write circuits and new data will be written into the RAM.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM54C864-80JS | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C864-80ZS | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C865 | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C865-10 | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C865-10JS | 65,536-Word X 8-Bit Multiport DRAM |
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|---|---|
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