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參數(shù)資料
| 型號(hào)： | MSM54C864-10ZS |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 65,536-Word X 8-Bit Multiport DRAM |
| 中文描述： | 65,536字× 8位多端口內(nèi)存 |
| 文件頁數(shù)： | 30/33頁 |
| 文件大?。?/td> | 368K |
| 代理商： | MSM54C864-10ZS |
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Semiconductor
MSM54C864
30/33
Write Transfer Cycle
A write transfer cycle transfers the contents of the SAM register into a selected row of the RAM
array. If the SAM data to be transferred must first be loaded through the SAM port, a pseudo
write transfer operation must precede the write transfer cycles.
Data transferred to SAM by read transfer cycle can be written to other address of RAM by write
transfer cycle.
A write transfer is invoked by holding
CAS
“l(fā)ow”,
WB
/
WE
“l(fā)ow” and
SE
“l(fā)ow” at the falling
edge of
RAS
.
The row address selected at the falling edge of
RAS
determines the RAM row address into which
the data will be transferred. The column address selected at the falling edge of
CAS
determines
the start address of the serial pointer of the SAM.
After the writetransfer is completed, the SIO lines are set in the input mode so that serial data
synchronized with the SC clock can be loaded.
When consecutive write transfer operations are performed, new data must not be written into
the serial register until the
RAS
cycle of the preceding write transfer is completed.
Consequently, the SC clock must be held at a constant V
IL
or V
IH
during the
RAS
cycle. A rising
edge of the SC clock is only allowed after the specified delay t
SRD
from the rising edge of
RAS
,
at which time a new row of data can be written in the serial register.
Pseudo Write Transfer Cycle
A pseudo write transfer cycle must be performed before loading data into the serial register after
a read transfer operation has been excuted. The only purpose of a pseudo write transfer is to
change the SAM port mode from output mode to input mode (A data transfer from SAM to RAM
does not occur).
After the serial register is loaded with new data, a write transfer cycle must be performed to
transfer the data from SAM to RAM. A pseudo write transfer is invoked by holding
CAS
“high”,
DT/OE “l(fā)ow”,
WB
/
WE
“l(fā)ow” and
SE
“high” at the falling edge of
RAS
. The timing conditions
are the same as the one for the write transfer cycle except for the state of
SE
at the falling edge of
RAS
.
Transfer Operation Without
CAS
During all transfer cycles, the
CAS
input clock must be cycled, so that the column address are
latched at the falling edge of
CAS
, to set the SAM tap location. If
CAS
was maintained at a
constant “high” level during a transfer cycle, the SAM pointer location would be undifined.
Therefore a transfer cycle with
CAS
held “high” is not allowed.
Normal Read Transfer Cycle After Normal Read Transfer Cycle
Another read transfer may be performed following the read transfer provided that a minimum
delay of 30 ns from the rising edge of the first clock SC is satisfied.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM54C864 | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C864-10 | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C864-10JS | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C864-70 | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C864-70JS | 65,536-Word X 8-Bit Multiport DRAM |
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參數(shù)描述 |
|---|---|
| MSM54V12222A-30TS-K | 制造商:OKI Semiconductor 功能描述:FIELD/FRAME/LINE MEMORY, 44 Pin, Plastic, TSOP |
| MSM54V12222B-25JDR17 | 制造商:ROHM Semiconductor 功能描述: |
| MSM54V12222B-25JSDR1 | 制造商:ROHM Semiconductor 功能描述: |
| MSM54V12222B-25T3-K7 | 制造商:ROHM Semiconductor 功能描述: |
| MSM54V12222B-25T3R17 | 制造商:ROHM Semiconductor 功能描述: |
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