參數(shù)資料
型號: MSM548262-70JS
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 262,144-Word x 8-Bit Multiport DRAM
中文描述: 262,144字× 8位多端口內(nèi)存
文件頁數(shù): 30/37頁
文件大?。?/td> 464K
代理商: MSM548262-70JS
Semiconductor
MSM548262
30/37
RAM PORT OPERATION
RAM Read Cycle:
RAS
falling edge ---
TRG
=
CAS
= "H", DSF = "L"
CAS
falling edge --- DSF = "L"
Row address is entered at the falling edge of
RAS
and column address at the falling edge of
CAS
to the device as in conventional DRAM. When the
WE
is "high" and
TRG
is "low" while
CAS
is
"low", the data outputs through DQ pins.
RAM Write Cycle:
RAS
falling edge ---
TRG
=
CAS
= "H", DSF = "L"
CAS
falling edge --- DSF = "L"
1) Write cycle with no mask:
RAS
falling edge --
WE
= "H"
If
WE
is set "low" at the falling edge of
CAS
after
RAS
goes "low" a write cycle is excuted. If
WE
is set "low" before the
CAS
falling edge, this cycle becomes an early write cycle, and all DQ pins
attain high impedance. All 8 data are latched on the falling edge of
CAS
.
If
WE
is set "low" after the
CAS
falling edge, this cycle becomes a late write cycle, and all 8 data
are latched on the falling edge of
WE
.
2) Write cycle with mask:
RAS
falling edge --
WE
= "L"
If
WE
is set "low" at the falling edge of
RAS
, the mask write mode can be invoked.
Mask data is loaded and used. The mask data on DQ1 - DQ8 is latched into the write mask register
at the falling edge of
RAS
. When the mask data is low, writing is inhibited into the RAM and the
mask data is high, data is written into the RAM. This mask data is in effect during the
RAS
cycle.
In page mode cycle the mask data is retained during page access.
相關(guān)PDF資料
PDF描述
MSM548262-70TS-K 262,144-Word x 8-Bit Multiport DRAM
MSM548262-80JS 262,144-Word x 8-Bit Multiport DRAM
MSM548262-80TS-K 262,144-Word x 8-Bit Multiport DRAM
MSM548262 262,144-Word ×8-Bit Multiport DRAM(256k字×8位多端口動態(tài)RAM)
MSM548263 262,144-Word ×8-Bit Multiport DRAM(256k字×8位多端口動態(tài)RAM)
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