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參數(shù)資料
| 型號： | MSM548128BL-80GS-K |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 131,072-Word X 8-Bit High-Speed PSRAM |
| 中文描述： | 131,072字× 8位高速移動存儲芯片 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 182K |
| 代理商： | MSM548128BL-80GS-K |
Semiconductor
MSM548128BL
7/12
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device.
2. All voltages are referenced to ground.
3. I
CC1
depends on output loading. Specified values are obtained with the output
open.
4. An initial pause of 100
μ
s is required after power-up followed by more than 8
initial cycles before proper device operation is achieved.
5. AC measurements assume t
T
= 5 ns.
6. t
CHZ
, t
WHZ
and t
OHZ
define the time at which the output achieves the open circuit
condition and is not referenced to output voltage levels.
7. In write cycles, the input data is latched at the earlier rising point of either
CE
or
WE
. Write operation is achieved when both
CE
and
WE
are low.
8. The I/O state remains at high impedance after
CE
goes low if the transition occurs
at the same time as or after the falling edge of
WE
.
9. Use
WE
or
OE
or both signals to disable the output before input data is applied
during a write cycle when the input is not the same.
10. Data input must be set to floating state before I/O becomes low impedance by
WE
or
OE
or both.
11. V
IH
(Min.) and V
IL
(Max.) are input timing reference levels for measurement. The
transition time is measured between V
IL
and V
IH
.
12. 512-cycle refresh must be applied within 15
μ
s after the end of self refreshing to
satisfy 512 cycles/8 ms.
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PDF描述 |
|---|---|
| MSM548128BL-80RS | 131,072-Word X 8-Bit High-Speed PSRAM |
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| MSM548262-60JS | 制造商:ROHM Semiconductor 功能描述: |
| MSM548262-60T3-K | 制造商:ROHM Semiconductor 功能描述: |
| MSM548262-60TK | 制造商:OK International 功能描述: |
| MSM548262-60TS-K | 制造商:ROHM Semiconductor 功能描述: |
| MSM548262-70JS | 制造商:ROHM Semiconductor 功能描述: |
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