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參數(shù)資料
| 型號： | MSM5416258A |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 262,144-Word×16-Bit DYNAMIC RAM(256K字×16位動態(tài)RAM) |
| 中文描述： | 262,144字× 16位動態(tài)隨機存儲器（256K字× 16位動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 263K |
| 代理商： | MSM5416258A |
8/21
Semiconductor
MSM5416258A
Notes:
1. All voltages are referenced to V
SS
.
2. This parameter is dependent upon the cycle rate.
3. This parameter is dependent upon the output loading. Specified values are obtained
with the output open.
4. An initial pause of 200
m
s is required after power-up, followed by any 8
RAS
cycles.
(Example :
RAS
-only-refresh) before proper device operation is achieved. In case of
using internal refresh counter, a minimum of 8
CAS
before
RAS
cycles instead of 8
RAS
cycles are required.
5. The AC characteristics assume t
T
= 5 ns.
6. V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring timing of input signals.
Also, transition times are measured between V
IH
and V
IL
.
7. Data outputs are measured with a load of 50 pF. DOUT reference levels: V
OH
/V
OL
=
2.0 V/1.4 V. Note that V
OL
is defined as 1.4 V when V
SS
* pins, pin 11 and pin 30, are
open. The data output measurements under V
OH
/V
OL
= 2.0 V/0.8 V are guaranteed
when V
SS
* pins, pin 11 and pin 30, are connected to GND.
8. t
REZ
(Max.), t
OFF
(Max.), t
WEZ
(Max.) and t
OEZ
(Max.) define the time at which the
outputs achieve the open circuit condition and are not referenced to output voltage
levels. This parameter is sampled and not 100% tested.
9. Either t
RCH
or t
RRH
must be satisfied for a read cycle.
10. These parameters are referenced to
CAS
leading edge of early write cycles and to
WE
leading edge in
OE
-controlled write cycles and read-modify-write cycles.
11. t
WCS
, t
RWD
, t
CWD
and t
AWD
are not restrictive operating parameters. They are included
in the data sheet as electrical characteristics only. If t
WCS
≥
t
WCS
(Min.), the cycle is an
early write cycle and the data out pins will remain open circuit throughout the entire
cycle. If t
RWD
≥
t
RWD
(Min.), t
CWD
≥
t
CWD
(Min.) and t
AWD
≥
t
AWD
(Min.), the cycle is
a read-modify-write cycle and the data out will contain data read from the selected cell.
If neither of the above sets of conditions is satisfied, the condition of the data out is
indeterminate.
12. Operation within the t
RCD
(Max.) limit insures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified
t
RCD
(Max.) limit, then access time is controlled by t
CAC
.
13. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only: If t
RAD
is greater than the specified
t
RAD
(Max.) limit, then access time is controlled by t
AA
.
14. Input levels at the AC testing are 3.0 V/0 V.
15. Addresses (A0 - A8) may be changed two times or less while
RAS
= V
IL
.
16. Addresses (A0 - A8) may be changed once or less while
CAS
= V
IH
and
RAS
= V
IL
.
17. This is guaranteed by design. (t
COH
= t
CAC
- output transition time). This parameter is
not 100% tested.
18. This parameter is dependent upon the number of address transitions. Specified values
are measured with a maximum of two transitions per address cycle in Fast Page Mode.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MSM5416258A-35J | 制造商:OK International 功能描述: |
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| MSM5416258B-30T3-K | 制造商:ROHM Semiconductor 功能描述: |
| MSM5416263-60G3-K | 制造商:ROHM Semiconductor 功能描述: |
| MSM5416263-60GS-K | 制造商:ROHM Semiconductor 功能描述: |
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