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參數(shù)資料
| 型號(hào)： | MSM5412222A |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 262,214-Word x 12-Bit Field Memory |
| 中文描述： | 262214字× 12位場(chǎng)記憶 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 68K |
| 代理商： | MSM5412222A |
OKI
Semiconductor
MSM5412222A
7
Power-up and Initialization
On power-up, the device is designed to begin proper operation after at least 100 us after V
CC
has stabilized to a value within the range of recommended operating conditions. After this
100 us stabilization interval, the following initialization sequence must be performed.
Because the read and write address counters are not valid after power-up, a minimum of 80
dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be
performed, followed by an RSTW operation and an RSTR operation, to properly initialize the
write and the read address pointer. Dummy write cycles/RSTW and dummy read
cycles/RSTR may occur simultaneously.
If these dummy read and write operations start while V
CC
and/or the substrate voltage has
not stabilized, it is necessary to perform an RSTR operation plus a minimum of 80 SRCK
cycles plus another RSTR operation, and an RSTW operation plus a minimum of 80 SRCK
cycles plus another RSTW operation to properly initialize read and write address pointers.
Old/New Data Access
There must be a minimum delay of 600 SWCK cycles between writing into memory and
reading out from memory. If reading from the first field starts with an RSTR operation, before
the start of writing the second field (before the next RSTW operation), then the data just
written will be read out.
The start of reading out the first field of data may be delayed past the beginning of writing in
the second field of data for as many as 70 SWCK cycles. If the RSTR operation for the first
field read-out occurs less than 70 SWCK cycles after the RSTW operation for the second
field write-in, then the internal buffering of the device assures that the first field will still be
read out. The first field of data that is read out while the second field of data is written is
called “old data”.
In order to read out “new data”, i.e., the second field written in, the delay between an RSTW
operation and an RSTR operation must be at least 600 SRCK cycles. If the delay between
RSTW and RSTR operations is more than 71 but less than 600 cycles, then the data read
out will be undetermined. It may be “old data” or “new” data, or a combination of old and new
data. Such a timing should be avoided.
Cascade Operation
The MSM5412222A is designed to allow easy cascading of multiple memory devices. This
provides higher storage depth, or a longer delay than can be achieved with only one
memory device.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM5412222B | 262,214-Word 】 12-Bit Field Memory |
| MSM5412222B-25JS | 262,214-Word 】 12-Bit Field Memory |
| MSM5412222B-25TS-K | 262,214-Word 】 12-Bit Field Memory |
| MSM5412222B-30JS | 262,214-Word 】 12-Bit Field Memory |
| MSM5412222B-30TS-K | 262,214-Word 】 12-Bit Field Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM5412222A-25TK | 制造商:OK International 功能描述: |
| MSM5412222B-25JS | 制造商:ROHM Semiconductor 功能描述: |
| MSM5412222B-25T3K-MT | 制造商:ROHM Semiconductor 功能描述: |
| MSM5412222B-25TS-K | 制造商:ROHM Semiconductor 功能描述: |
| MSM5416258A-35J | 制造商:OK International 功能描述: |
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