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參數(shù)資料
| 型號： | MSM518121A-10ZS |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 131,072-Word X 8-Bit Multiport DRAM |
| 中文描述： | 131,072字× 8位多端口內(nèi)存 |
| 文件頁數(shù)： | 27/33頁 |
| 文件大?。?/td> | 368K |
| 代理商： | MSM518121A-10ZS |
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Semiconductor
MSM518121A
27/33
Write Mask Data / Data Input and Mask Data : W1 / IO1 - W8 / IO8
W1/ IO1 to W8 / IO8 have the functions of both Input/Output and a control input signal. As the
standard DRAM’s I/O pins, input data on the W1/IO1 to W8/IO8 are written into the RAM port
during the write cycle. The input data is latched at the falling edge of either
CAS
or
WB
/
WE
,
whichever occurs later. The RAM data out buffers, which will output read data from the W1/IO1
to W8 /IO8 pins, become low impedance state after the specified access times from
RAS
,
CAS
,
DT
/
OE
and column address are satisfied and the output data will remain vaild as long as
CAS
and
DT
/
OE
are kept “l(fā)ow”. The outputs will return to the high-impedance state at the rising edge
of either
CAS
or
DT
/
OE
, whichever occurs earlier.
In addition to the conventional I/O functions, the W1/IO1 to W8/IO8 have the funnction to set
the mask data, which select mask input pins out of eight input pins, W1/ IO1 to W8/IO8, at the
falling edge of
RAS
. Data is written in to the DRAM on data lines where the write-mask data is
a logic “1”. Writing is inhibited on data lines where the write-mask data is a logic “0”. The write-
mask data is valid for only one cycle.
Serial Clock : SC
SC is a main serial cycle contorol input signal. All operations of the SAM port are synchronized
with the serial clock SC. Data is shifted in or out of the SAM registers at the rising edge of SC. In
a serial read, the output data becomes valid on the SIO pins after the maximum specified serial
access time t
SCA
from the rising edge of SC.
The serial lock SC also increments the 8 bits serial pointer which is used to select the SAM address.
The pointer address is incremented in a wrap-around mode to select sequential locations after
the setting location which is determined by the column address in the read transfer cycle. When
the pointer reaches the most significant address location (Decimal 255), the next SC clock will
place it at the least significant address location (Decimal 0).
The serial clock SC must be held data constant V
IH
or V
IL
level during read/pseudo write/write
transfer operations and should not be clocked while the SAM port is in the standby mode to
prevent the SAM pointer from being incremented.
Serial Enable :
SE
The
SE
is a serial access enable control and serial read/write control input signal. In a serial read
cycle,
SE
is used as an output control. In a serial write cycle,
SE
is used as a write enable control.
When
SE
is “high”, serial access is disable, however, the serial address pointer location is still
incremented when SC is clocked even when
SE
is “high”.
Serial Input / Output : SIO1 - SIO8
Serial input/output mode is determined by the most recent read, write or pseudo write transfer
cycle. When a read transfer cycle is performed, the SAM port is in the output mode. When a write
or pseudo write transfer cycle is performed, the SAM port is switched from output mode to input
mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM518121A-70 | 131,072-Word X 8-Bit Multiport DRAM |
| MSM518121A-70JS | 131,072-Word X 8-Bit Multiport DRAM |
| MSM518121A-70ZS | 131,072-Word X 8-Bit Multiport DRAM |
| MSM518121A-80 | 131,072-Word X 8-Bit Multiport DRAM |
| MSM518121A-80JS | 131,072-Word X 8-Bit Multiport DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM518121A-70 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word X 8-Bit Multiport DRAM |
| MSM518121A-70JS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word X 8-Bit Multiport DRAM |
| MSM518121A-70ZS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word X 8-Bit Multiport DRAM |
| MSM518121A-80 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word X 8-Bit Multiport DRAM |
| MSM518121A-80JS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word X 8-Bit Multiport DRAM |
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