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參數(shù)資料
| 型號： | MSM514252A |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 262,144-Word x 4-Bit Multiport DRAM |
| 中文描述： | 262,144字× 4位多端口內(nèi)存 |
| 文件頁數(shù)： | 31/33頁 |
| 文件大?。?/td> | 358K |
| 代理商： | MSM514252A |
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MSM514252A
Semiconductor
31/33
POWER-UP
Power must be applied to the
RAS
and
DT
/
OE
input signals to pull them "high" before or at the
same time as the V
CC
supply is turned on. After power-up, a pause of 200
μ
seconds (minimum)
is required with
RAS
and
DT
/
OE
held "high".
After the pause, a minimum of 8
RAS
and 8 SC dummy cycles must be performed to stabilize the
internal circuitry, before valid read, write or transfer operations can begin. During the
initialization period, the
DT
/
OE
signal must be held "high". If the internal refresh counter is
used, a minimum 8
CAS
-before-
RAS
initialization cycles are required instead of 8
RAS
cycles.
Initial State After Power-up
When power is achieved with
RAS
,
CAS
,
DT
/
OE
and
WB
/
WE
held "high" the internal state of
the MSM514252A is automatically set as follows.
SAM port -------------------
Input mode
Write mask register ------
Write mode
TAP pointer----------------
Invalid
However, the initial state can not be guaranteed for various power-up conditions and input
signal levels. Therefore, it is recommended that the initial state be set after the initialization of
the device is performed (200
μ
seconds pause followed by a minimum of 8
RAS
cycles and 8 SC
cycles) and before valid operations begin.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM514252A-10ZS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:262,144-Word x 4-Bit Multiport DRAM |
| MSM514252A-70JS | 制造商:ROHM Semiconductor 功能描述: |
| MSM514252A-80ZS | 制造商:ROHM Semiconductor 功能描述: |
| MSM514256B-60J | 制造商:OK International 功能描述: |
| MSM514256C | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:262,144-Word x 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
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