參數(shù)資料
型號: MSM51257CLL
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 32,768-Word ×8-Bit CMOS STATIC RAM(32k字×8位靜態(tài)RAM)
中文描述: 32,768詞× 8位的CMOS靜態(tài)RAM(32K的字× 8位靜態(tài)RAM)的
文件頁數(shù): 7/12頁
文件大小: 175K
代理商: MSM51257CLL
7/12
Semiconductor
MSM51257CLL
Write Cycle
Parameter
Min.
100
0
75
5
40
0
90
90
5
Max.
35
Min.
55
0
45
5
30
0
50
50
5
Max.
25
Symbol
Unit
Write Cycle Time
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Setup Time
Data Hold Time
WE
to Output in High-Z
CS
to End of Write
Address Valid to End of Write
Output Active from End of Write
t
WC
t
AS
t
WP
t
WR
t
DS
t
DH
t
WHZ
t
CW
t
AW
t
WLZ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MSM51257CLL-70 MSM51257CLL-85 MSM51257CLL-10
Min.
70
0
55
5
35
0
65
65
5
5
MSM51257CLL-55
Min.
85
0
70
5
40
0
75
75
Max.
30
Max.
30
(V
CC
= 5 V ±10%, Ta = 0C to 70C)
A
0
- A
14
CS
WE
I/O (D
IN
)
I/O (D
OUT
)
t
WC
t
WP
t
AW
t
AS
t
CW
t
WR
t
DS
t
DH
t
WHZ
t
WLZ
Stable Data-in
Notes:
1. A write cycle occurs during the overlap of
CS
= "L" and
WE
= "L".
2.
OE
may be either of "H" or "L" in the write cycle.
3. t
AS
is specified from
CS
= "L" or
WE
= "L", whichever occurs last.
4. t
WP
is an overlap time of
CS
= "L" and
WE
= "L".
5. t
WR
, t
DS
and t
DH
are specified from
CS
= "H" or
WE
= "H", whichever occurs first.
6. t
WHZ
is specified by the time when DATA output is floating, not defined by the
output level.
7. When I/O pins are in the output mode, don't apply the inverted input signal to the
output pins.
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