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參數(shù)資料
| 型號(hào)： | MSC8144TVT1000A |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 133 MHz, OTHER DSP, PBGA783 |
| 封裝： | 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783 |
| 文件頁(yè)數(shù)： | 38/80頁(yè) |
| 文件大?。?/td> | 1250K |
| 代理商： | MSC8144TVT1000A |
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Electrical Characteristics
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
43
Using these waveforms, the definitions are as follows:
1.
The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a peak-to-peak voltage
(VPP) swing of A – B.
2.
The differential output signal of the transmitter, VOD, is defined as VTD – VTD.
3.
The differential input signal of the receiver, VID, is defined as VRD – VRD.
4.
The differential output signal of the transmitter and the differential input signal of the receiver each range from A – B
to –(A – B).
5.
The peak value of the differential transmitter output signal and the differential receiver input signal is A – B.
6.
The value of the differential transmitter output signal and the differential receiver input signal is 2
× (A – B) V
PP.
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common
mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 V and 2.0 V. Using these values,
the peak-to-peak voltage swing of the signals TD and TD is 500 mVPP. The differential output signal ranges between 500 mV
and –500 mV. The peak differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mVPP.
Note:
AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at three baud
rates (a total of six cases) are described. The parameters for the AC electrical specifications are guided by the XAUI
electrical interface specified in Clause 47 of IEEE Std 802.3ae-2002. XAUI has similar application goals to
serial RapidIO. The goal of this standard is that electrical designs for serial RapidIO can reuse electrical designs for
XAUI, suitably modified for applications at the baud intervals and reaches described herein.
2.6.5.3
Equalization
With the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. Effects such
as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye
opening at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be
used. The most common equalization techniques that can be used are:
A passive high pass filter network placed at the receiver. This is often referred to as passive equalization.
The use of active circuits in the receiver. This is often referred to as adaptive equalization.
2.6.5.4
Transmitter Specifications
LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section. The differential return
loss, S11, of the transmitter in each case shall be better than
–10 dB for (baud frequency)/10 < freq(f) < 625 MHz, and
–10 dB + 10log(f/625 MHz) dB for 625 MHz
≤ freq(f) ≤ baud frequency
The reference impedance for the differential return loss measurements is 100
Ω resistive. Differential return loss includes
contributions from internal circuitry, packaging, and any external components related to the driver. The output impedance
requirement applies to all valid output levels. It is recommended that the 20–80% rise/fall time of the transmitter, as measured
at the transmitter output, have a minimum value 60 ps in each case. It is also recommended that the timing skew at the output
of an LP-Serial transmitter between the two signals comprising a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50
GB, and 15 ps at 3.125 GB.
Table 25. Short Run Transmitter AC Timing Specifications—1.25 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Output Voltage
VO
–0.40
2.30
V
Voltage relative to COMMON of either signal
comprising a differential pair
Differential Output Voltage
VDIFFPP
500
1000
mVPP
Deterministic Jitter
JD
0.17
UIPP
Total Jitter
JT
0.35
UIPP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSC8144SVT1000B | 133 MHz, OTHER DSP, PBGA783 |
| MSC8144VT1000A | 133 MHz, OTHER DSP, PBGA783 |
| MSC8144SVT800A | 133 MHz, OTHER DSP, PBGA783 |
| MSC8156SVT1000B | 0-BIT, OTHER DSP, PBGA783 |
| MSC8254TVT800B | 0-BIT, OTHER DSP, PBGA783 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSC8144TVT1000B | 制造商:Freescale Semiconductor 功能描述:PACSUN REV2.1 NON-E - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA |
| MSC8144TVT800A | 功能描述:IC DSP QUAD 800MHZ 783FCBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8144TVT800B | 制造商:Freescale Semiconductor 功能描述:PACSUN REV2.1 NON-E - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA |
| MSC8144VT1000A | 功能描述:IC DSP QUAD 1GHZ 783FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8144VT1000B | 制造商:Freescale Semiconductor 功能描述:DSP 32-Bit 1GHz 1000MIPS 783-Pin FCBGA 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA 制造商:Freescale 功能描述:DSP 32-Bit 1GHz 1000MIPS 783-Pin FCBGA |
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