- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69037 > MSC8101M1250F (FREESCALE SEMICONDUCTOR INC) 64-BIT, 62.5 MHz, OTHER DSP, PBGA332 PDF資料下載
參數(shù)資料
| 型號(hào)： | MSC8101M1250F |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 64-BIT, 62.5 MHz, OTHER DSP, PBGA332 |
| 封裝： | 17 X 17 MM, LIDDED FLIP CHIP, LEAD FREE, PLASTIC, BGA-332 |
| 文件頁(yè)數(shù)： | 51/104頁(yè) |
| 文件大小： | 1811K |
| 代理商： | MSC8101M1250F |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)當(dāng)前第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)
MSC8101 Technical Data, Rev. 18
2-10
Freescale Semiconductor
Physical and Electrical Specifications
2.6.4.2 Power-On Reset Flow
Asserting the PORESET external pin initiates the power-on reset flow.
Note:
PORESET
and TRST must be asserted externally for the duration of the power-up sequence.
As Table 2-13 shows, the MSC8101 has five configuration pins, four of which are multiplexed with the SC140
EONCE Event (EE[0–1], EE[4–5]) pins and the fifth of which is the RSTCONF pin. These pins are sampled at the
rising edge of PORESET. In addition to these configuration pins, three (MODCK[1–3]) pins are sampled by the
MSC8101. The signals on these pins and the MODCK_H value in the Hard Reset Configuration Word determine
the PLL locking mode, by defining the ratio between the DSP clock, the bus clocks, and the CPM clock
frequencies.
Table 2-13.
External Configuration Signals
Pin
Description
Settings
RSTCONF
Reset Configuration
Input line sampled by the MSC8101 at the rising edge of
PORESET.
0
Reset Configuration Master.
1
Reset Configuration Slave.
DBREQ/ EE0
EONCE Event Bit 0
Input line sampled after SC140 core PLL locks. Holding EE0
high when PORESET is deasserted puts the SC140 into
Debug mode.
0
SC140 starts the normal processing
mode after reset.
1
SC140 enters Debug mode immediately
after reset.
HPE/EE1
Host Port Enable
Input line sampled at the rising edge of PORESET. If
asserted, the Host port is enabled, the system data bus is
32-bit wide, and the Host
must program the reset
configuration word.
0
Host port disabled (hardware reset
configuration enabled).
1
Host port enabled.
BTM[0–1]/
EE[4–5]
Boot Mode
Input lines sampled at the rising edge of PORESET, which
determine the MSC8101 Boot mode.
00
MSC8101 boots from external memory.
01
MSC8101 boots from HDI16.
10
Reserved.
11
Reserved.
Table 2-14.
Reset Timing
No.
Characteristics
Expression
Min
Max
Unit
1
Required external PORESET duration minimum
CLKIN = 18 MHz
CLKIN = 75 MHz
16
/ CLKIN
888.8
213.3
—
ns
2
Delay from deassertion of external PORESET to deassertion of
internal PORESET
CLKIN = 18 MHz
CLKIN = 75 MHz
1024
/ CLKIN
56.89
13.65
s
3
Delay from deassertion of internal PORESET to SPLL lock
SPLLMFCLK = 18 MHz
SPLLMFCLK = 25 MHz
800
/ SPLLMFCLK
44.4
32.0
s
4
Delay from SPLL lock to DLL lock
DLL enabled
— BCLK = 18 MHz
— BCLK = 75 MHz
DLL disabled
3073
/ BLCK
—
170.72
40.97
0.0
s
ns
5
Delay from SPLL lock to HRESET deassertion
DLL enabled
— BCLK = 18 MHz
— BCLK = 75 MHz
DLL disabled
— BCLK = 18 MHz
— BCLK = 75 MHz
3585
/ BLCK
512
/ BLCK
199.17
47.5
28.4
6.83
s
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSC8101M1500F | 64-BIT, 75 MHz, OTHER DSP, PBGA332 |
| MSC8101VT1250F | 64-BIT, 62.5 MHz, OTHER DSP, PBGA332 |
| MSC8101VT1500F | 64-BIT, 75 MHz, OTHER DSP, PBGA332 |
| MSC8101M1375F | 64-BIT, 68.75 MHz, OTHER DSP, PBGA332 |
| MSC8126VT8000 | 0-BIT, 500 MHz, OTHER DSP, PBGA431 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSC8101M1375C | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Network Digital Signal Processor |
| MSC8101M1375F | 功能描述:DSP 16BIT 275MHZ CPM 332-FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8101M1500F | 功能描述:DSP 16BIT 300MHZ CPM 332-FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8101UG/D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor |
| MSC8101VT1250F | 功能描述:IC DSP 16BIT 250MHZ 332-FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。