參數(shù)資料
型號(hào)： MSC7116VM1000
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 17/60頁(yè)
文件大小： 0K
描述： DSP 16BIT W/DDR CTRLR 400-MAPBGA
標(biāo)準(zhǔn)包裝： 90
系列： StarCore
類型： 定點(diǎn)
接口： 主機(jī)接口，I²C，UART
時(shí)鐘速率： 266MHz
非易失內(nèi)存： ROM（8 kB）
芯片上RAM： 400kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 400-LFBGA
供應(yīng)商設(shè)備封裝： 400-MAPBGA（17x17）
包裝： 托盤
MSC7116 Data Sheet, Rev. 13
Electrical Characteristics
Freescale Semiconductor
24
2.5.3
Reset Timing
The MSC7116 device has several inputs to the reset logic. All MSC7116 reset sources are fed into the reset controller, which
takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause
a reset. Table 14 describes the reset sources.
Table 15 summarizes the reset actions that occur as a result of the different reset sources.
2.5.3.1
Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after
external power to the MSC7116 reaches at least 2/3 VDD.
Table 14. Reset Sources
Name
Direction
Description
Power-on reset
(PORESET)
Input
Initiates the power-on reset flow that resets the MSC7116 and configures various attributes of the
MSC7116. On PORESET, the entire MSC7116 device is reset. SPLL and DLL states are reset,
HRESET is driven, the SC1400 extended core is reset, and system configuration is sampled. The
system is configured only when PORESET is asserted.
External Hard
reset (HRESET)
Input/ Output
Initiates the hard reset flow that configures various attributes of the MSC7116. While HRESET is
asserted, HRESET is an open-drain output. Upon hard reset, HRESET is driven and the SC1400
extended core is reset.
Software
watchdog reset
Internal
When the MSC7116 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
Bus monitor
reset
Internal
When the MSC7116 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
JTAG EXTEST,
CLAMP, or
HIGHZ command
Internal
When a Test Access Port (TAP) executes an EXTEST, CLAMP, or HIGHZ command, the TAP logic
asserts an internal reset signal that generates an internal soft reset sequence.
Table 15. Reset Actions for Each Reset Source
Reset Action/Reset Source
Power-On Reset
(PORESET)
Hard Reset
(HRESET)
Soft Reset
(SRESET)
External only
External or
Internal (Software
Watchdog or Bus
Monitor)
JTAG Command:
EXTEST, CLAMP,
or HIGHZ
Configuration pins sampled (refer to Section 2.5.3.1 for
details).
Yes
No
PLL and clock synthesis states Reset
Yes
No
HRESET Driven
Yes
No
Software watchdog and bus time-out monitor registers
Yes
Clock synthesis modules (STOPCTRL, HLTREQ, and
HLTACK) reset
Yes
Extended core reset
Yes
Peripheral modules reset
Yes
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